LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
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entity spec_register is
    port (clk, rst : in std_logic;
        A0, A1 : in std_logic;
        Data : in std_logic_vector(6 downto 0);
        Q : out std_logic_vector(6 downto 0));
end spec_register;
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architecture beh of spec_register is
    signal Qreg : std_logic_vector(6 downto 0);
    ----------------------------------------------------------
begin
    Q <= Qreg;
    process (clk)
    begin
        if (clk'event and clk = '1') then
            if (rst='0') THEN
                Qreg <= "0000000";

            elsif A0 = '0' and A1 = '1' then --LR1
                Qreg <= '0' & Qreg(6 downto 1);
            elsif A0 = '1' and A1 = '0' then --CR1
                Qreg <= Qreg(0) & Qreg(6 downto 1);
            elsif A0 = '1' and A1 = '1' then --AL2
                Qreg <= Qreg(6) & Qreg(3 downto 0) & "00";
            elsif A0 = '0' and A1 = '0' then --saugojimas
                Qreg <= Data;
            end if;
        end if;
    end process;
end beh;