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Jun 26th, 2017
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VHDL 0.58 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. entity flygplats is
  5.  
  6.         port(r:in std_logic_vector(3 downto 0);
  7.                  y:out std_logic_vector(2 downto 0));
  8.  
  9. end flygplats;
  10.  
  11. architecture beteende of flygplats is
  12. begin
  13.  
  14.         flyg_d: process (r, y)
  15.         begin
  16.  
  17.                 if r(0) = '1' then y<= "001";
  18.                 elsif r(1) = '1' then y<= "010";
  19.                 elsif r(2) = '1' then y<= "011";
  20.                 elsif r(3) = '1' then y<= "100";
  21.                 else y<= "000";
  22.  
  23.                 end if;
  24.         end process flyg_d;
  25. end beteende;
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