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Jun 28th, 2018
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VHDL 0.31 KB | None | 0 0
  1. process (CLK, RES_IN, MODE_UP) begin
  2.     if RES_IN = '1' then
  3.         cntval <= "000000000000000000000000000";
  4.     end if;
  5.     if (CLK'event and clk='1' and MODE_UP = '1') then
  6.         cntval <= cntval+1;
  7.     else
  8.         if (CLK'event and clk='1' and MODE_UP = '0') then
  9.             cntval <= cntval-1;
  10.         else
  11.         end if;
  12.     end if;
  13. end process;
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