dcfm j flipflop

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jk is
port(inp:in std_logic_vector(2 downto 0);
     Q:in std_logic_vector(0 downto 0);
     r:out std_logic_vector(0 downto 0));
end jk;
architecture bev of jk is
begin
process(inp)
begin
case inp is
when "000"=>r<=Q;
when "101"=>r<="0";
when "110"=>r<="1";
when "111"=>r<=(not Q);
when others=>r<="U";
end case;
end process;
end bev;