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-- Company:
-- Engineer:
--
-- Create Date:    18:15:58 07/07/2012
-- Design Name:
-- Module Name:    h3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.filter_pkg.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity h3 is
generic(
        index : integer
        --rnd_v : hash_array
        );
port (
      rnd_v : in hash_array;
      data_in : in std_logic_vector(max_msg_bits-1 downto 0);
        data_out :  out std_logic_vector(num_hash_bits-1 downto 0)
        );

end h3;



architecture Behavioral of h3 is

signal and_value : row_array;
signal digest_int : std_logic_vector(num_hash_bits-1 downto 0):=(others => '0'); -- intermediate digest
--signal digest : std_logic_vector(num_hash_bits-1 downto 0):=(others => '0');

begin

process(data_in)
variable digest : std_logic_vector(num_hash_bits-1 downto 0);
begin
digest := (others => '0');
    for  b in 0 to  max_msg_length-1 loop  -- loop on the 8 bits of input byte
        for  i in 0 to  7 loop  -- loop on the 8 bits of input byte
            for  j in 0 to num_hash_bits-1 loop
            and_value(b)(i)(j) <=  rnd_v(index)(b)(i)(j) and data_in(b*8+i);  -- rnd_v(index)(i)(j)
            end loop;
            digest := digest  xor and_value(b)(i);
        end loop ;
    end loop;

    data_out <= digest;

end process ;


end Behavioral;