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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3.  * Copyright (C) 2018 PHYTEC Messtechnik GmbH
  4.  * Author: Christian Hemp <c.hemp@phytec.de>
  5.  */
  6.  
  7. /dts-v1/;
  8. #include "imx6q.dtsi"
  9. #include "imx6qdl-phytec-phycore-som.dtsi"
  10. #include "imx6qdl-phytec-mira.dtsi"
  11. #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
  12. #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
  13. #include "imx6qdl-phytec-peb-wlbt-01.dtsi"
  14. #include <dt-bindings/sound/fsl-imx-audmux.h>
  15.  
  16. / {
  17.     model = "PHYTEC phyBOARD-Mira Quad full featured with NAND";
  18.     compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
  19.              "phytec,imx6qdl-pcm058", "fsl,imx6q";
  20.  
  21.     chosen {
  22.         linux,stdout-path = &uart2;
  23.     };
  24. };
  25.  
  26. #define SSI_TEST_MASTER
  27. /*
  28.  * port 4 is datasheet port 5 (aud5)
  29.  * port 6 is datasheet port 7 (ssi3)
  30.  */
  31. #define AUDMUX_EXT_PORT 4
  32. #define AUDMUX_INT_PORT 6
  33. #define AUDMUX_INT_PORT_NAME port5
  34. &audmux {
  35.         status = "okay";
  36.     ssi3 {
  37.          fsl,audmux-port = <AUDMUX_INT_PORT>;
  38.          fsl,port-config = <
  39. #ifdef SSI_TEST_MASTER
  40.     IMX_AUDMUX_V2_PTCR_SYN 
  41. #else
  42.     (IMX_AUDMUX_V2_PTCR_TFSDIR |
  43.     IMX_AUDMUX_V2_PTCR_TFSEL(AUDMUX_EXT_PORT) |
  44.     IMX_AUDMUX_V2_PTCR_TCLKDIR |
  45.     IMX_AUDMUX_V2_PTCR_TCSEL(AUDMUX_EXT_PORT) |
  46.     IMX_AUDMUX_V2_PTCR_SYN 
  47.     )
  48. #endif
  49.              IMX_AUDMUX_V2_PDCR_RXDSEL(AUDMUX_EXT_PORT)
  50.     >;
  51.      };
  52.  
  53.      AUDMUX_INT_PORT_NAME {
  54.          fsl,audmux-port = <AUDMUX_EXT_PORT>;
  55.          fsl,port-config = <
  56. #ifdef SSI_TEST_MASTER
  57.              (IMX_AUDMUX_V2_PTCR_TFSDIR |
  58.              IMX_AUDMUX_V2_PTCR_TFSEL(AUDMUX_INT_PORT) |
  59.              IMX_AUDMUX_V2_PTCR_TCLKDIR |
  60.              IMX_AUDMUX_V2_PTCR_TCSEL(AUDMUX_INT_PORT) |
  61.             IMX_AUDMUX_V2_PTCR_SYN 
  62.          )
  63. #else
  64.     IMX_AUDMUX_V2_PTCR_SYN 
  65. #endif
  66.              IMX_AUDMUX_V2_PDCR_RXDSEL(AUDMUX_INT_PORT)
  67.          >;
  68.      };
  69. };
  70.  
  71.  
  72. //&ssi1 {
  73. //  status = "okay";
  74. //};
  75.  
  76. &ssi3 {
  77.      pinctrl-names = "default";
  78.      pinctrl-0 = <&pinctrl_audmux>;
  79.      fsl,mode = "i2s-master";
  80.      status = "okay";
  81.  
  82.      // select the a clock parent suitable for 48000 Hz sampling rate
  83.      assigned-clocks = <&clks IMX6QDL_CLK_SSI3_SEL>, <&clks IMX6QDL_CLK_SSI3>;
  84.      assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
  85.      assigned-clock-rates = <0>, <49152000>;
  86. };
  87.  
  88. / {
  89.      codec_test: codec_test {
  90.          compatible = "linux,snd-soc-dummy";
  91.          #sound-dai-cells = <0>;
  92.      };
  93.  
  94.  
  95.      sound@2 {
  96.          compatible = "simple-audio-card";
  97.          simple-audio-card,name = "loopback-ssi-test";
  98.          simple-audio-card,format="dsp_a";
  99.  
  100. #ifdef SSI_TEST_MASTER
  101.          simple-audio-card,frame-master = <&sound2_ssi>;
  102.          simple-audio-card,bitclock-master = <&sound2_ssi>;
  103. #else
  104.          simple-audio-card,frame-master = <&codec_test>;
  105.          simple-audio-card,bitclock-master = <&codec_test>;
  106. #endif
  107.              sound2_ssi: simple-audio-card,cpu {
  108.                  sound-dai = <&ssi3>;
  109.                  system-clock-frequency = <1536000>;
  110.                  dai-tdm-slot-num = <8>;
  111.                  dai-tdm-slot-width = <16>;
  112.              };
  113.              sound2codec: simple-audio-card,codec {
  114.                  sound-dai = <&codec_test>;
  115.              };
  116.      };
  117.  
  118. };
  119.  
  120. &iomuxc {
  121.  
  122.     pinctrl-names = "default";
  123.  
  124.     pinctrl_audmux: audmuxgrp {
  125.         fsl,pins = <
  126.             MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0 // wandboard  jp1.20
  127.             MX6QDL_PAD_DISP0_DAT16__AUD5_TXC    0x130b0 // wandboard, jp1.14
  128.             MX6QDL_PAD_DISP0_DAT17__AUD5_TXD    0x110b0 // wandboard  jp1.16
  129.             MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS   0x130b0 // wandboard  jp1.18
  130.             MX6QDL_PAD_GPIO_19__CCM_CLKO1           0x130b0 // wandboard  jp4.18
  131.         >;
  132.     };
  133. };
  134.  
  135. &can1 {
  136.     status = "okay";
  137. };
  138.  
  139. &dim_gpio_leds {
  140.     status = "okay";
  141. };
  142.  
  143. &fec {
  144.     status = "okay";
  145. };
  146.  
  147. &gpmi {
  148.     status = "okay";
  149. };
  150.  
  151. &hdmi {
  152.     status = "okay";
  153. };
  154.  
  155. &i2c1 {
  156.     status = "okay";
  157. };
  158.  
  159. &i2c2 {
  160.     status = "okay";
  161. };
  162.  
  163. &i2c_rtc {
  164.     status = "okay";
  165. };
  166.  
  167. &leddim {
  168.     status = "okay";
  169. };
  170.  
  171. &m25p80 {
  172.     status = "okay";
  173. };
  174.  
  175. &pcie {
  176.     status = "okay";
  177. };
  178.  
  179. &uart3 {
  180.     status = "okay";
  181. };
  182.  
  183. &usbh1 {
  184.     status = "okay";
  185. };
  186.  
  187. &usbotg {
  188.     status = "okay";
  189. };
  190.  
  191. &usdhc1 {
  192.     status = "okay";
  193. };
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