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buildOpts.c for ASUS AM1I-A - 09-APR-2020 (changes 33913-20)

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* This file is part of the coreboot project. */
  3.  
  4. /**
  5.  * @file
  6.  *
  7.  * AMD User options selection for a Brazos platform solution system
  8.  *
  9.  * This file is placed in the user's platform directory and contains the
  10.  * build option selections desired for that platform.
  11.  *
  12.  * For Information about this file, see @ref platforminstall.
  13.  *
  14.  */
  15.  
  16. #include <stdlib.h>
  17.  
  18. #include <vendorcode/amd/agesa/f16kb/AGESA.h>
  19.  
  20. /*  Include the files that instantiate the configuration definitions.  */
  21. #include <vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h>
  22. #include <vendorcode/amd/agesa/f16kb/Include/GnbInterface.h>
  23. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h>
  24. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h>
  25. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h>
  26. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h>
  27. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h>
  28. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h>
  29. /* AGESA nonesense: the next three headers depend on heapManager.h */
  30. #include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h>
  31. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
  32. #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
  33. /* These tables are optional and may be used to adjust memory timing settings */
  34. #include <vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h>
  35. #include <vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h>
  36.  
  37. /*  Select the CPU family.  */
  38. #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
  39.  
  40. /*  Select the CPU socket type.  */
  41. #define INSTALL_G34_SOCKET_SUPPORT  FALSE
  42. #define INSTALL_C32_SOCKET_SUPPORT  FALSE
  43. #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
  44. #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
  45. #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
  46. #define INSTALL_FS1_SOCKET_SUPPORT  FALSE
  47. #define INSTALL_FM1_SOCKET_SUPPORT  FALSE
  48. #define INSTALL_FP2_SOCKET_SUPPORT  FALSE
  49. #define INSTALL_FT1_SOCKET_SUPPORT  FALSE
  50. #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
  51. #define INSTALL_FM2_SOCKET_SUPPORT  FALSE
  52. #define INSTALL_FT3_SOCKET_SUPPORT  TRUE
  53.  
  54. #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
  55.   #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
  56.     #undef INSTALL_FT3_SOCKET_SUPPORT
  57.     #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
  58.   #endif
  59. #endif
  60.  
  61. //#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
  62. //#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
  63. //#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
  64. #define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
  65. //#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
  66. //#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
  67. //#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
  68. #define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
  69. #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
  70. //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
  71. #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
  72. //#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
  73. #define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
  74. #define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
  75. #define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
  76. #define BLDOPT_REMOVE_CRAT                     TRUE
  77. #define BLDOPT_REMOVE_CDIT                     TRUE
  78. #define BLDOPT_REMOVE_DMI                      TRUE
  79. //#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
  80. //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
  81. //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
  82. //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
  83. //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
  84. //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
  85.  
  86. //This element selects whether P-States should be forced to be independent,
  87. // as reported by the ACPI _PSD object. For single-link processors,
  88. // setting TRUE for OS to support this feature.
  89.  
  90. //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
  91.  
  92. #define BLDCFG_PCI_MMIO_BASE    CONFIG_MMCONF_BASE_ADDRESS
  93. #define BLDCFG_PCI_MMIO_SIZE    CONFIG_MMCONF_BUS_NUMBER
  94. /* Build configuration values here.
  95.  */
  96. #define BLDCFG_VRM_CURRENT_LIMIT                 15000
  97. #define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
  98. #define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT         21000
  99. #define BLDCFG_VRM_SVI_OCP_LEVEL                 BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
  100. #define BLDCFG_PLAT_NUM_IO_APICS                 3
  101. #define BLDCFG_GNB_IOAPIC_ADDRESS                0xFEC20000
  102. #define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
  103. #define BLDCFG_MEM_INIT_PSTATE                   0
  104.  
  105. #define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_DESKTOP
  106.  
  107. #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
  108. #define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
  109. #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
  110. #define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
  111. #define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
  112. #define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
  113. #define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
  114. #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
  115. #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    TRUE
  116. #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
  117. #define BLDCFG_MEMORY_POWER_DOWN                  TRUE
  118. #define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
  119. #define BLDCFG_ONLINE_SPARE                       FALSE
  120. #define BLDCFG_BANK_SWIZZLE                       TRUE
  121. #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
  122. #define BLDCFG_MEMORY_CLOCK_SELECT                DDR1866_FREQUENCY
  123. #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
  124. #define BLDCFG_IGNORE_SPD_CHECKSUM                TRUE
  125. #define BLDCFG_USE_BURST_MODE                     FALSE
  126. #define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
  127. #define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
  128. #define BLDCFG_ECC_REDIRECTION                    FALSE
  129. #define BLDCFG_SCRUB_DRAM_RATE                    0
  130. #define BLDCFG_SCRUB_L2_RATE                      0
  131. #define BLDCFG_SCRUB_L3_RATE                      0
  132. #define BLDCFG_SCRUB_IC_RATE                      0
  133. #define BLDCFG_SCRUB_DC_RATE                      0
  134. #define BLDCFG_ECC_SYMBOL_SIZE                    4
  135. #define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
  136. #define BLDCFG_ECC_SYNC_FLOOD                     FALSE
  137. #define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
  138. #define BLDCFG_1GB_ALIGN                          FALSE
  139. //#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
  140. #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
  141.                                                          // core for C-state entry requests. A value
  142.                                                          // of 0 in this field specifies that the core
  143.                                                          // does not trap any IO addresses for C-state entry.
  144.                                                          // Values greater than 0xFFF8 results in undefined behavior.
  145.  
  146. #define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
  147. #define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
  148. #define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
  149.  
  150. //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
  151. #define BLDCFG_CFG_ABM_SUPPORT                    TRUE
  152.  
  153. #ifdef PCIEX_BASE_ADDRESS
  154. #define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
  155. #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
  156. #endif
  157.  
  158. #define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
  159.  
  160. // Specify the default values for the VRM controlling the VDDNB plane.
  161. // If not specified, the values used for the core VRM will be applied
  162. #define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
  163. #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
  164. #define BLDCFG_VRM_SLEW_RATE                      10000
  165. #define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
  166. #define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
  167. #define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
  168.  
  169. #if CONFIG(GFXUMA)
  170. #define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
  171. #define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
  172. #define OPTION_GFX_INIT_SVIEW                     FALSE
  173. #endif
  174.  
  175. #define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
  176.  
  177. #define BLDCFG_IOMMU_SUPPORT                      FALSE
  178.  
  179. #define BLDCFG_CFG_GNB_HD_AUDIO               TRUE
  180. //#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
  181. //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
  182. //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
  183.  
  184. /*  Process the options...
  185.  * This file include MUST occur AFTER the user option selection settings
  186.  */
  187. /*
  188.  * Customized OEM build configurations for FCH component
  189.  */
  190. // #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
  191. // #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
  192. // #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
  193. // #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
  194. // #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
  195. // #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
  196. // #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
  197. // #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
  198. // #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
  199. // #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
  200. // #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
  201. // #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
  202. // #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
  203. // #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
  204. // #define BLDCFG_AZALIA_SSID                    0x780D1022
  205. // #define BLDCFG_SMBUS_SSID                     0x780B1022
  206. // #define BLDCFG_IDE_SSID                       0x780C1022
  207. // #define BLDCFG_SATA_AHCI_SSID                 0x78011022
  208. // #define BLDCFG_SATA_IDE_SSID                  0x78001022
  209. // #define BLDCFG_SATA_RAID5_SSID                0x78031022
  210. // #define BLDCFG_SATA_RAID_SSID                 0x78021022
  211. // #define BLDCFG_EHCI_SSID                      0x78081022
  212. // #define BLDCFG_OHCI_SSID                      0x78071022
  213. // #define BLDCFG_LPC_SSID                       0x780E1022
  214. // #define BLDCFG_SD_SSID                        0x78061022
  215. // #define BLDCFG_XHCI_SSID                      0x78121022
  216. // #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
  217. // #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
  218. // #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
  219. // #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
  220. // #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
  221. // #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
  222. // #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
  223. // #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
  224. // #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
  225. // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
  226. // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
  227.  
  228. CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
  229. {
  230.   { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
  231.   { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
  232.   { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
  233.   { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
  234.   { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
  235.   { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
  236.   { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
  237.   { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
  238.   { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
  239.   { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
  240.   { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
  241.   { CPU_LIST_TERMINAL }
  242. };
  243.  
  244. #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
  245.  
  246.                   // This is the delivery package title, "BrazosPI"
  247.                   // This string MUST be exactly 8 characters long
  248. #define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
  249.  
  250.                   // This is the release version number of the AGESA component
  251.                   // This string MUST be exactly 12 characters long
  252. #define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
  253.  
  254. /* MEMORY_BUS_SPEED */
  255. #define DDR400_FREQUENCY   200     ///< DDR 400
  256. #define DDR533_FREQUENCY   266     ///< DDR 533
  257. #define DDR667_FREQUENCY   333     ///< DDR 667
  258. #define DDR800_FREQUENCY   400     ///< DDR 800
  259. #define DDR1066_FREQUENCY   533    ///< DDR 1066
  260. #define DDR1333_FREQUENCY   667    ///< DDR 1333
  261. #define DDR1600_FREQUENCY   800    ///< DDR 1600
  262. #define DDR1866_FREQUENCY   933    ///< DDR 1866
  263. #define DDR2100_FREQUENCY   1050   ///< DDR 2100
  264. #define DDR2133_FREQUENCY   1066   ///< DDR 2133
  265. #define DDR2400_FREQUENCY   1200   ///< DDR 2400
  266. #define UNSUPPORTED_DDR_FREQUENCY       1201 ///< Highest limit of DDR frequency
  267.  
  268. /* QUANDRANK_TYPE*/
  269. #define QUADRANK_REGISTERED             0 ///< Quadrank registered DIMM
  270. #define QUADRANK_UNBUFFERED             1 ///< Quadrank unbuffered DIMM
  271.  
  272. /* USER_MEMORY_TIMING_MODE */
  273. #define TIMING_MODE_AUTO                0 ///< Use best rate possible
  274. #define TIMING_MODE_LIMITED             1 ///< Set user top limit
  275. #define TIMING_MODE_SPECIFIC            2 ///< Set user specified speed
  276.  
  277. /* POWER_DOWN_MODE */
  278. #define POWER_DOWN_BY_CHANNEL           0 ///< Channel power down mode
  279. #define POWER_DOWN_BY_CHIP_SELECT       1 ///< Chip select power down mode
  280.  
  281. /*
  282.  * Agesa optional capabilities selection.
  283.  * Uncomment and mark FALSE those features you wish to include in the build.
  284.  * Comment out or mark TRUE those features you want to REMOVE from the build.
  285.  */
  286.  
  287. #define DFLT_SMBUS0_BASE_ADDRESS            0xB00
  288. #define DFLT_SMBUS1_BASE_ADDRESS            0xB20
  289. #define DFLT_SIO_PME_BASE_ADDRESS           0xE00
  290. #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
  291. #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
  292. #define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
  293. #define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
  294. #define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
  295. #define DFLT_SPI_BASE_ADDRESS               0xFEC10000
  296. #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
  297. #define DFLT_HPET_BASE_ADDRESS              0xFED00000
  298. #define DFLT_SMI_CMD_PORT                   0xB0
  299. #define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
  300. #define DFLT_GEC_BASE_ADDRESS               0xFED61000
  301. #define DFLT_AZALIA_SSID                    0x780D1022
  302. #define DFLT_SMBUS_SSID                     0x780B1022
  303. #define DFLT_IDE_SSID                       0x780C1022
  304. #define DFLT_SATA_AHCI_SSID                 0x78011022
  305. #define DFLT_SATA_IDE_SSID                  0x78001022
  306. #define DFLT_SATA_RAID5_SSID                0x78031022
  307. #define DFLT_SATA_RAID_SSID                 0x78021022
  308. #define DFLT_EHCI_SSID                      0x78081022
  309. #define DFLT_OHCI_SSID                      0x78071022
  310. #define DFLT_LPC_SSID                       0x780E1022
  311. #define DFLT_SD_SSID                        0x78061022
  312. #define DFLT_XHCI_SSID                      0x78121022
  313. #define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
  314. #define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
  315. #define DFLT_FCH_GPP_LINK_CONFIG            PortA4
  316. #define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
  317. #define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
  318. #define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
  319. #define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
  320. #define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
  321. #define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
  322. #define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
  323. #define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
  324. //#define BLDCFG_IR_PIN_CONTROL 0x33
  325.  
  326. GPIO_CONTROL   imba180_gpio[] = {
  327.     {183, Function1, GpioIn | GpioOutEnB | PullUpB},
  328.     {-1}
  329. };
  330. //#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&imba180_gpio[0])
  331.  
  332. // The following definitions specify the default values for various parameters in which there are
  333. // no clearly defined defaults to be used in the common file.  The values below are based on product
  334. // and BKDG content, please consult the AGESA Memory team for consultation.
  335. #define DFLT_SCRUB_DRAM_RATE            (0)
  336. #define DFLT_SCRUB_L2_RATE              (0)
  337. #define DFLT_SCRUB_L3_RATE              (0)
  338. #define DFLT_SCRUB_IC_RATE              (0)
  339. #define DFLT_SCRUB_DC_RATE              (0)
  340. #define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
  341. #define DFLT_VRM_SLEW_RATE              (5000)
  342.  
  343. /* AGESA nonsense: this header depends on the definitions above */
  344. #include <PlatformInstall.h>
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