lab4sumator2biti

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-- Company:
-- Engineer:
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-- Create Date: 03/23/2018 02:20:45 PM
-- Design Name:
-- Module Name: sum2b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sum2b is
Port (
           x : in std_logic_vector(1 downto 0);
           y: in std_logic_vector(1 downto 0);
           tin: in std_logic;
           sum : out std_logic_vector(1 downto 0);
           P : out std_logic;
           G : out std_logic);
end sum2b;


architecture Behavioral of sum2b is

signal pp : std_logic_vector(1 downto 0);
signal qq : std_logic_vector(1 downto 0);

signal t0 : std_logic;


begin

qq(0) <= x(0) and y(0);
qq(1) <= x(1) and y(0);

pp(0) <= x(0) or y(0);
pp(1) <= x(1) or y(1);


sum(0) <= x(0) xor y(0) xor tin;
sum(1) <= x(1) xor y(1) xor tin;

P <= pp(0) or pp(1);
G <= qq(1) or (pp(1) and qq(0));

t0 <= qq(0) or (pp(0) and tin);

end Behavioral;