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okgmt

180041209_vhdl

Jan 7th, 2021
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  1. -- 180041209
  2. -- Zibran Zarif Amio
  3. library ieee;
  4. use ieee.std_logic.all;
  5.  
  6. entity ent_comp is
  7.   port ( m,n :in bit (7 downto 0);
  8.          clk, reset :in bit;
  9.          comp_result :out (7 downto 0));
  10. end ent_comp;
  11.  
  12. architecture bhv of ent_comp is
  13. begin
  14. process p_comp is
  15. begin
  16. if (clk = 0)
  17. process pp_comp is
  18. begin
  19. if (m=n)
  20.   comp_result <= '001';
  21. else if (m>n)
  22.   comp_result <= '010';
  23. else if (m<n)
  24.   comp_result <= '100';
  25. else
  26.   comp_result <= '000';
  27. end if;
  28. end process;
  29.  
  30. else if(reset = 0)
  31. comp_result <= '000';
  32. end if;
  33. end process;
  34. end bhv;
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