180041209_vhdl

-- 180041209
-- Zibran Zarif Amio
library ieee;
use ieee.std_logic.all;

entity ent_comp is
  port ( m,n :in bit (7 downto 0);
         clk, reset :in bit;
         comp_result :out (7 downto 0));
end ent_comp;

architecture bhv of ent_comp is
begin
process p_comp is
begin
if (clk = 0)
process pp_comp is
begin
if (m=n)
  comp_result <= '001';
else if (m>n)
  comp_result <= '010';
else if (m<n)
  comp_result <= '100';
else
  comp_result <= '000';
end if;
end process;

else if(reset = 0)
comp_result <= '000';
end if;
end process;
end bhv;