cv2

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-- Company:
-- Engineer:
--
-- Create Date:   16:05:01 10/07/2013
-- Design Name:
-- Module Name:   C:/Users/TEMP.WIN-XLYL2SP2PLD.014/Desktop/-p/cvikoMoje/dekoder/decodertest.vhd
-- Project Name:  dekoder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dekoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY decodertest IS
END decodertest;

ARCHITECTURE behavior OF decodertest IS

    -- Component Declaration for the Unit Under Test (UUT)

 signal T_I: std_logic_vector(1 downto 0):="00";
  signal T_O: std_logic_vector(3 downto 0);

    COMPONENT dekoder
    PORT(
         I : IN  std_logic_vector(1 downto 0);
         O : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal I : std_logic_vector(1 downto 0) := (others => '0');

    --Outputs
   signal O : std_logic_vector(3 downto 0);
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   constant <clock>_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: dekoder PORT MAP (
          T_I,T_O
        );
          process
          variable err_ent : integer :=0;
            begin
                 -- case "00"
                 wait for 10 ns;
                 T_I <= "00";
                 wait for 1 ns;
                 assert (T_0="0001") report "chyba pri 00"
                 severity report;
                 if (T_0/="0001") then err_cnt:=err_cnt + 1;
                 end if;

                 -- case "01"
                 wait for 10 ns;
                 T_I <= "01";
                 wait for 1 ns;
                 assert (T_0="0010") report "chyba pri 01"
                 severity report;
                 if (T_0/="0010") then err_cnt:=err_cnt + 1;
                 end if;

                 -- case "10"
                 wait for 10 ns;
                 T_I <= "10";
                 wait for 1 ns;
                 assert (T_0="0110") report "chyba pri 10"
                 severity report;
                 if (T_0/="0110") then err_cnt:=err_cnt + 1;
                 end if;

                 -- case "11"
                 wait for 10 ns;
                 T_I <= "11";
                 wait for 1 ns;
                 assert (T_0="0000") report "chyba pri 11"
                 severity report;
                 if (T_0/="0000") then err_cnt:=err_cnt + 1;
                 end if;

            if (err_cnt = 0) then
            assert false
            report "vsetko ok"
            severity note;
            else
            assert true;
            report "nejaka chyba"
            severity error;
            end if;
      wait;
   end process;

END behavior;