library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Quiz is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           Pulsante1 : in  STD_LOGIC;
           Pulsante2 : in  STD_LOGIC;
           Display : out  STD_LOGIC_VECTOR (0 to 6);
              stato : out STD_LOGIC_VECTOR (0 to 2);
              cont : out STD_LOGIC_VECTOR (0 to 3));
end Quiz;

architecture Behavioral of Quiz is

component GestionePulsanti is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           P1 : in  STD_LOGIC;
           P2 : in  STD_LOGIC;
           seg_out : out  STD_LOGIC_VECTOR (0 to 3);
              state_debug : out STD_LOGIC_VECTOR (0 to 2);
              count_debug : out STD_LOGIC_VECTOR (0 to 3));
end component;

component Display7Segmenti is
    Port ( num : in  STD_LOGIC_VECTOR (0 to 3);
           segments : out  STD_LOGIC_VECTOR (0 to 6));
end component;

signal seg_in: STD_LOGIC_VECTOR (0 to 3);
-- utilizzo seg_in come segnale di output di "GestionePulsanti"
-- che va in input a "Display7Segmenti"

begin

seq: GestionePulsanti port map (rst, clk, Pulsante1, Pulsante2, seg_in, stato, cont);
seg: Display7Segmenti port map (seg_in, display);

end Behavioral;