library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BINtoBCD_tb is
--  Port ( );
end BINtoBCD_tb;

architecture Behavioral of BINtoBCD_tb is

component BINtoBCD is
    Port ( c  : in STD_LOGIC;
           S3 : in STD_LOGIC;
           S2 : in STD_LOGIC;
           S1 : in STD_LOGIC;
           S0 : in STD_LOGIC;
           bcd1 : out STD_LOGIC_VECTOR(3 downto 0);
           bcd0 : out STD_LOGIC_VECTOR(3 downto 0));
end component;

signal input: STD_LOGIC_VECTOR (4 downto 0);
signal bcd1 : STD_LOGIC_VECTOR(3 downto 0);
signal bcd0 : STD_LOGIC_VECTOR(3 downto 0);
signal succes : boolean := true;

begin

decoder : BINtoBCD port map (
    s0 => input(0),
    s1 => input(1),
    s2 => input(2),
    s3 => input(3),
    c => input(4),
    bcd0 => bcd0,
    bcd1 => bcd1
);

process
begin
    for i in 0 to 31 loop
        wait for 5 ns;
        input <= std_logic_vector(to_unsigned(i, input'length));
        wait for 5 ns;
        if unsigned(bcd0) /= i mod 10 or unsigned(bcd1) /= i / 10 then
            succes <= false;
        end if;

    end loop;

    wait;
end process;

end Behavioral;