library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SIPO_main is
    Port ( CLK : in STD_LOGIC;
           S : in STD_LOGIC;
           Q : inout STD_LOGIC_VECTOR (3 downto 0));
end SIPO_main;

architecture Behavioral of SIPO_main is

begin
process (CLK)
    begin
    if (rising_edge(CLK))then
        Q(3 downto 1) <= Q(2 downto 0);
        Q(0) <= S;
    end if;
end process;

end Behavioral;