library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity VideoBuffer is
    port(
        clk             :in Std_Logic;
        reset               :in Std_Logic;
        inputSelector   :in Std_Logic_Vector(1 downto 0);
        dataIn          :in Std_Logic_Vector(7 downto 0);
        dataLoad            :in Std_Logic;
        output          :out Std_Logic
    );
end videobuffer;

architecture Behavioral of VideoBuffer is
    signal A, B, C, D           :Std_Logic_Vector(7 downto 0);
    signal outputSelector   :Std_Logic_Vector(1 downto 0);
    signal step                 :Integer;
begin
    process (clk, reset, inputSelector, dataIn, dataLoad, A, B, C, D, outputSelector, step) is
    begin
        if reset = '0' then
            A <= "00000000";
            B <= "00000000";
            C <= "00000000";
            D <= "00000000";
            output <= '0';
            outputSelector <= "11";
            step <= 7;
        else
            if dataload = '1' then
                case inputSelector is
                    when "00"   => A <= dataIn; B <= B; C <= C; D <= D;
                    when "01"   => B <= dataIn; A <= A; C <= C; D <= D;
                    when "10"   => C <= dataIn; A <= A; B <= B; D <= D;
                    when "11"   => D <= dataIn; A <= A; B <= B; C <= C;
                    when others => A <= A; B <= B; C <= C; D <= D;
                end case;
            else
                A <= A;
                B <= B;
                C <= C;
                D <= D;
            end if;
            if rising_edge(clk) then
                if step < 7 then
                    step <= step + 1;
                    outputSelector <= outputSelector;
                else
                    step <= 0;
                    outputSelector <= outputSelector + 1;
                end if;
            else
                step <= step;
                outputSelector <= outputSelector;
            end if;
            case outputSelector is
                when "00"   => output <= A(step);
                when "01"   => output <= B(step);
                when "10"   => output <= C(step);
                when "11"   => output <= D(step);
                when others => output <= '0';
            end case;
        end if;
    end process;
end Behavioral;