LucaSkywalker

DoubleDabble_tb.vhd

Nov 15th, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  6.  
  7. ENTITY DoubleDabble_tb IS
  8.     port (Data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
  9.             Clk_out: OUT STD_LOGIC);
  10. END DoubleDabble_tb;
  11.  
  12. ARCHITECTURE behavior OF DoubleDabble_tb IS
  13.  
  14. constant Clk_period : time := 10 ns;
  15.  BEGIN
  16.              
  17.    Clk_process :process
  18.    begin
  19.         Clk_out <= '0';
  20.         wait for Clk_period/2;
  21.         Clk_out <= '1';
  22.         wait for Clk_period/2;
  23.    end process;
  24.  
  25.    stim_proc: process
  26.    begin        
  27.         Data_out <= "11010111";
  28.    wait;
  29.    end process;
  30. END;
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