entity guess_game is
port(
    inputs : in std_logic_vector(7 downto 0);
    set : in std_logic; -- Set predefined value
    show : in std_logic; -- Show predefined value
    try : in std_logic; -- Evaluate guess
    hex1 : out std_logic_vector(6 downto 0); -- 7-seg ones
    hex10: out std_logic_vector(6 downto 0) -- 7-seg tens
);
end guess_game;

architecture tester of guess_game is
signal s1 : std_logic_vector (7 downto 0); --guess_input (Secret)
signal s2 : std_logic_vector (1 downto 0); --Compare_logic
signal s3 : std_logic_vector (7 downto 0); --Mux_output
signal s4, s5: std_logic_vector (6 downto 0); -- Display 1 og 2 output, og endelig output

begin

UT_latch: entity hej_latch port map (input => inputs, set => set, secret => s1);
UT_compare: entity compare_logic port map (try => try, input => inputs, secret => s1, comp => s2);
UT_mux2to1: entity mux_2to1 port map (bin => inputs, latch => s1, show => show, outbin => s3);
UT_display1: entity segment_decoder port map (bin => s3 (3 downto 0), seg => s4);
UT_display2: entity segment_decoder port map (bin => s3 (7 downto 4), seg => s5);
UT_mux4to1: entity mux_4to1 port map (sseg => (s5 & s4), CL => s2, HEX(6 downto 0) => hex1, HEX(13 downto 7) => hex10);
end tester;