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  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3. --USE ieee.std_logic_unsigned.ALL;
  4.  
  5. ENTITY Zadatak4_tb IS
  6. END Zadatak4_tb;
  7.  
  8. ARCHITECTURE behavior OF Zadatak4_tb IS
  9.  
  10.     -- Component Declaration for the Unit Under Test (UUT)
  11.  
  12.     COMPONENT Zadatak4
  13.     PORT(
  14.          inOK : IN  std_logic;
  15.          inHAZ : IN  std_logic;
  16.          inRST : IN  std_logic;
  17.          iCLK : IN  std_logic;
  18.          oRED : OUT  std_logic_vector(1 downto 0);
  19.          oYELLOW : OUT  std_logic_vector(1 downto 0);
  20.          oGREEN : OUT  std_logic_vector(1 downto 0)
  21.         );
  22.     END COMPONENT;
  23.    
  24.  
  25.    --Inputs
  26.    signal inOK : std_logic := '0';
  27.    signal inHAZ : std_logic := '0';
  28.    signal inRST : std_logic := '0';
  29.    signal iCLK : std_logic := '0';
  30.  
  31.     --Outputs
  32.    signal oRED : std_logic_vector(1 downto 0);
  33.    signal oYELLOW : std_logic_vector(1 downto 0);
  34.    signal oGREEN : std_logic_vector(1 downto 0);
  35.  
  36.    -- Clock period definitions
  37.    constant iCLK_period : time := 10 ns;
  38.  
  39. BEGIN
  40.  
  41.     -- Instantiate the Unit Under Test (UUT)
  42.    uut: Zadatak4 PORT MAP (
  43.           inOK => inOK,
  44.           inHAZ => inHAZ,
  45.           inRST => inRST,
  46.           iCLK => iCLK,
  47.           oRED => oRED,
  48.           oYELLOW => oYELLOW,
  49.           oGREEN => oGREEN
  50.         );
  51.  
  52.    -- Clock process definitions
  53.    iCLK_process :process
  54.    begin
  55.         iCLK <= '0';
  56.         wait for iCLK_period/2;
  57.         iCLK <= '1';
  58.         wait for iCLK_period/2;
  59.    end process;
  60.  
  61.  
  62.    -- Stimulus process
  63.    stim_proc: process
  64.    begin       
  65.      
  66.         inRST <= '0';
  67.       wait for 100 ns;
  68.         inRST <= '1';
  69.  
  70.         inHAZ <= '1';
  71.         inOK <= '0';
  72.        
  73.         wait for iCLK_period;
  74.         inOK <= '1';
  75.        
  76.         wait for 4*12*iCLK_period;
  77.        
  78.         inHAZ <= '0';
  79.  
  80.       wait;
  81.    end process;
  82.  
  83. END;
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