LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.ALL;

ENTITY Zadatak4_tb IS
END Zadatak4_tb;

ARCHITECTURE behavior OF Zadatak4_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Zadatak4
    PORT(
         inOK : IN  std_logic;
         inHAZ : IN  std_logic;
         inRST : IN  std_logic;
         iCLK : IN  std_logic;
         oRED : OUT  std_logic_vector(1 downto 0);
         oYELLOW : OUT  std_logic_vector(1 downto 0);
         oGREEN : OUT  std_logic_vector(1 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal inOK : std_logic := '0';
   signal inHAZ : std_logic := '0';
   signal inRST : std_logic := '0';
   signal iCLK : std_logic := '0';

    --Outputs
   signal oRED : std_logic_vector(1 downto 0);
   signal oYELLOW : std_logic_vector(1 downto 0);
   signal oGREEN : std_logic_vector(1 downto 0);

   -- Clock period definitions
   constant iCLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Zadatak4 PORT MAP (
          inOK => inOK,
          inHAZ => inHAZ,
          inRST => inRST,
          iCLK => iCLK,
          oRED => oRED,
          oYELLOW => oYELLOW,
          oGREEN => oGREEN
        );

   -- Clock process definitions
   iCLK_process :process
   begin
        iCLK <= '0';
        wait for iCLK_period/2;
        iCLK <= '1';
        wait for iCLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin

        inRST <= '0';
      wait for 100 ns;
        inRST <= '1';

        inHAZ <= '1';
        inOK <= '0';

        wait for iCLK_period;
        inOK <= '1';

        wait for 4*12*iCLK_period;

        inHAZ <= '0';

      wait;
   end process;

END;