entity guess_gametester is
port(
    SW : in std_logic_vector(7 downto 0);
    KEY : in std_logic_vector (3 downto 0); -- Set predefined value
    HEX0 : out std_logic_vector(6 downto 0); -- 7-seg ones
    HEX1: out std_logic_vector(6 downto 0) -- 7-seg tens
);
end guess_gametester;

architecture test_test of guess_gametester is
begin

UTEST: entity guess_game port map (inputs => SW, set => KEY(0), show => KEY(1), try => KEY(2), hex1 => HEX0, hex10 => HEX1);

end test_test;