LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY test_bench2 IS
generic( numOfBits : integer :=16);
END ENTITY test_bench2;
ARCHITECTURE behavioral OF test_bench2 IS

signal tbdin_i : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal tbdin_q : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal tbclk : std_logic;
signal tbdoutI : std_logic_vector(15 downto 0);
signal tbdoutQ : std_logic_vector(15 downto 0);

signal tbrst : std_logic;
signal tbrfd : std_logic;

signal tbdv :  std_logic;
signal tbsign :  std_logic := '1';

signal syncro_rst : std_logic;
signal syncro_rfd : std_logic;

component top IS
    Port ( clk : in std_logic;
    dv : in std_logic;
    codeI : in std_logic_vector(15 downto 0);
    codeQ : in std_logic_vector(15 downto 0);
    doutI : out std_logic_vector(15 downto 0);
    doutQ : out std_logic_vector(15 downto 0));
END component;

component ReadFile is
    generic( numOfBits : integer :=16;
    file_i : string := "C:\Users\thug\Desktop\FPGA\lab13v2\data_i.txt";
    file_q : string := "C:\Users\thug\Desktop\FPGA\lab13v2\data_q.txt");
port( data_i : out std_logic_vector ((numOfBits-1) downto 0) := (others => '0');
    data_q : out std_logic_vector ((numOfBits-1) downto 0) := (others => '0');
    dv: out std_logic;
    rst : in std_logic;
    rfd : in std_logic;
    clk : in std_logic);
end component;

component WriteFile_full IS
    generic( numOfBits : integer :=16;
    file_i : string := "C:\Users\thug\Desktop\FPGA\lab13v2\doutput_i.txt";
    file_q : string := "C:\Users\thug\Desktop\FPGA\lab13v2\doutput_q.txt");
port( clk,dv,sign : in std_logic;
     DataIn_I : in std_logic_vector ((numOfBits-1) downto 0);
     DataIn_Q : in std_logic_vector ((numOfBits-1) downto 0));
end component;

-----------------------------------------------------------------

BEGIN
generate_clk : process begin
    loop
        tbclk <= '0';
        wait for 25 ns;
        tbclk <= '1';
        wait for 25 ns;
        end loop;
end process;

generate_tbrst : process begin
    tbrst <= '1', '0' after 175 ns;
    wait;
end process;

generate_tbrfd : process begin
    tbrfd <= '0', '1' after 200 ns;
    wait;
end process;


process(tbclk) begin
    if rising_edge(tbclk) then
        syncro_rst <= tbrst;
        syncro_rfd <= tbrfd;
    end if;
end process;

read : ReadFile
port map (clk => tbclk,
    rfd => syncro_rfd,
    rst => syncro_rst,
    dv => tbdv,
    data_i => tbdin_i,
    data_q => tbdin_q);

write : WriteFile_full
port map ( clk => tbclk,
    dv => tbdv,
    sign => tbsign,
    DataIn_I => tbdoutI,
    DataIn_Q => tbdoutQ);

lab_13 : top
port map ( clk => tbclk,
    dv => tbdv,
    codeI => tbdin_i,
    codeQ => tbdin_q,
    doutI => tbdoutI,
    doutQ => tbdoutQ);

END  behavioral;