Lab #2 - Dean Nguyen

--Lab #2: XOR_Gate (Dean Nguyen)--

--Libraries--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

--Entity--
ENTITY XOR_Gate IS
    GENERIC (   SIZE        : INTEGER   := 8); --Generic with default value
    PORT        (   INPUT       : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Input by # of inputs
                    OUTPUT  : OUT STD_LOGIC); --Output
END XOR_Gate;

--Archtiecture--
ARCHITECTURE behavioral OF XOR_Gate IS
    SIGNAL xor_sig : STD_LOGIC; --Signal to copy output of each loop to
    SIGNAL xor_init: STD_LOGIC; --Signal to copy output of each loop to
BEGIN

    xor_proc    : PROCESS(xor_sig, xor_init)

    BEGIN

        xor_sig <= INPUT(0) XOR INPUT(1); --Start XORing the first two bits
        IF (SIZE > 2) THEN--If more than 2 bits
            FOR i IN 1 TO (SIZE - 1) LOOP --Loop
                xor_init <= xor_sig; --Set sig to another placeholder sig
                xor_sig <= INPUT(i) XOR xor_init; --Set sig to XOR of specific input bit and placeholder sig
            END LOOP;
        ELSE
            NEXT;
        END IF;

    END PROCESS;

    OUTPUT <= xor_sig; --Set output to sig

END behavioral;

---------------------------------------------------------------------------

--Lab #2: Shift_Reg (Dean Nguyen)--

--Libraries--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

--Entity--
ENTITY Shift_Reg IS
    GENERIC (   SIZE                                    : INTEGER   := 8); --Generic with default value
    PORT        (   CLK, RESET_N, LOAD, SERIAL_IN   : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
                    SEED                                    : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
                    PARALLEL_OUT                        : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
END Shift_Reg;

--Architecture--
ARCHITECTURE behavioral OF Shift_Reg IS
    SIGNAL SHIFT    : STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Signal to copy input to
BEGIN

    shifter : PROCESS(CLK, RESET_N) --Process where clock and reset changes

    BEGIN

        IF (RESET_N = '0') THEN --If reset on
            SHIFT <= (OTHERS => '0'); --Shift is 0
        ELSIF (RISING_EDGE(CLK)) THEN --For every clock's rising edge
            IF (LOAD = '1') THEN --If load on
                SHIFT <= SEED; --Load seed
            ELSE
                SHIFT((SIZE - 1) DOWNTO 1) <= SHIFT((SIZE - 2) DOWNTO 0); --Shift
                SHIFT(0) <= SERIAL_IN; --Insert serial_in to LSB
            END IF;
        END IF;

    END PROCESS;

    PARALLEL_OUT <= SHIFT; --Output signal

END behavioral;

---------------------------------------------------------------------------

--Lab #2: Shift_Reg_TB (Dean Nguyen)--

--Libraries--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

--Entity--
ENTITY Shift_Reg_TB IS
END Shift_Reg_TB;

--Architecture--
ARCHITECTURE behavioral OF Shift_Reg_TB IS

--Components--
COMPONENT Shift_Reg
    GENERIC (   SIZE                                    : INTEGER   := 8); --Generic with default value
    PORT        (   CLK, RESET_N, LOAD, SERIAL_IN   : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
                    SEED                                    : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
                    PARALLEL_OUT                        : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
END COMPONENT;

--Inputs--
SIGNAL CLK_TB           : STD_LOGIC := '0';
SIGNAL RESET_N_TB       : STD_LOGIC := '0';
SIGNAL LOAD_TB          : STD_LOGIC := '0';
SIGNAL SERIAL_IN_TB : STD_LOGIC := '0';
SIGNAL SEED_TB          : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');

--Outputs--
SIGNAL PARALLEL_OUT_TB  : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');

--Constants--
CONSTANT period     : TIME := 20ns;

BEGIN

--Clock Process--
clock : PROCESS

    BEGIN

        CLK_TB <= NOT CLK_TB;
        WAIT FOR period/2;

    END PROCESS;

--Reset Process--
reset : PROCESS

    BEGIN

        WAIT FOR 2*period;
        RESET_N_TB <= '1';
        WAIT;

    END PROCESS;

    uut: Shift_Reg
        GENERIC MAP (
            SIZE => 8)
        PORT MAP (
            CLK => CLK_TB,
            RESET_N => RESET_N_TB,
            LOAD => LOAD_TB,
            SERIAL_IN => SERIAL_IN_TB,
            SEED => SEED_TB,
            PARALLEL_OUT => PARALLEL_OUT_TB);

    stimulus    : PROCESS
    BEGIN

        SEED_TB <= "00001111";
        SERIAL_IN_TB <= '1';
        RESET_N_TB <= '0';
        WAIT FOR 2*period;
        RESET_N_TB <= '1';
        LOAD_TB <= '1';
        WAIT FOR 2*period;
        FOR i IN 0 TO 9 LOOP
            LOAD_TB <= '0';
            WAIT FOR 2*period;
        END LOOP;

    END PROCESS;

END behavioral;