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- -- Tarefa09.vhd
- -----------------------------------------------------------------------------------
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- ENTITY Tarefa09 IS
- PORT(
- ctrl, clock: IN STD_LOGIC; -- ctrl: define se sera crescente ou descrescente | 0 - crescente, 1 - decrescente
- q0, q1: OUT STD_LOGIC
- );
- END Tarefa09;
- ARCHITECTURE Arc OF Tarefa09 IS
- COMPONENT FFT IS
- PORT(
- clk: IN STD_LOGIC;
- q: OUT STD_LOGIC
- );
- END COMPONENT;
- COMPONENT Mux2x1 IS
- PORT(
- a, b: IN STD_LOGIC;
- sel: IN STD_LOGIC;
- x: OUT STD_LOGIC
- );
- END COMPONENT;
- SIGNAL sq0, sq00, sq1: STD_LOGIC;
- BEGIN
- I0: FFT PORT MAP(clock,sq0);
- I1: Mux2x1 PORT MAP(NOT sq0,sq0,ctrl,sq00);
- I2: FFT PORT MAP(sq00,sq1);
- q0 <= sq0;
- q1 <= sq1;
- END Arc;
- -----------------------------------------------------------------------------------
- -- FFT.vhd
- -----------------------------------------------------------------------------------
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- ENTITY FFT IS
- PORT(
- clk: IN STD_LOGIC;
- q: OUT STD_LOGIC
- );
- END FFT;
- ARCHITECTURE Arc OF FFT IS
- SIGNAL sq: STD_LOGIC;
- BEGIN
- PROCESS(clk)
- BEGIN
- IF(clk'event AND clk='1') THEN -- clk'event: é o evento de subida/descida.
- q <= (not sq);
- END IF;
- END PROCESS;
- END Arc;
- -----------------------------------------------------------------------------------
- -- Mux2x1.vhd
- -----------------------------------------------------------------------------------
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- ENTITY Mux2x1 IS
- PORT(
- a, b: IN STD_LOGIC;
- sel: IN STD_LOGIC;
- x: OUT STD_LOGIC
- );
- END Mux2x1;
- ARCHITECTURE arc OF Mux2x1 IS
- BEGIN
- PROCESS(a,b,sel)
- BEGIN
- IF(sel = '0') THEN
- x <= a;
- ELSE
- x <= b;
- END IF;
- END PROCESS;
- END arc;
- -----------------------------------------------------------------------------------
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