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Oct 20th, 2013
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VHDL 1.91 KB | None | 0 0
  1. -- Tarefa09.vhd
  2. -----------------------------------------------------------------------------------
  3. LIBRARY IEEE;
  4. USE IEEE.STD_LOGIC_1164.ALL;
  5.  
  6. ENTITY Tarefa09 IS
  7.     PORT(
  8.         ctrl, clock: IN STD_LOGIC; -- ctrl: define se sera crescente ou descrescente | 0 - crescente, 1 - decrescente
  9.         q0, q1: OUT STD_LOGIC
  10.     );
  11. END Tarefa09;
  12.  
  13. ARCHITECTURE Arc OF Tarefa09 IS
  14.     COMPONENT FFT IS
  15.         PORT(
  16.             clk: IN STD_LOGIC;
  17.             q: OUT STD_LOGIC
  18.         );
  19.     END COMPONENT;
  20.    
  21.     COMPONENT Mux2x1 IS
  22.         PORT(
  23.             a, b: IN STD_LOGIC;
  24.             sel: IN STD_LOGIC;
  25.             x: OUT STD_LOGIC
  26.         );
  27.     END COMPONENT;
  28.    
  29.     SIGNAL sq0, sq00, sq1: STD_LOGIC;
  30.    
  31.     BEGIN
  32.        
  33.         I0: FFT PORT MAP(clock,sq0);
  34.         I1: Mux2x1 PORT MAP(NOT sq0,sq0,ctrl,sq00);
  35.         I2: FFT PORT MAP(sq00,sq1);
  36.        
  37.         q0 <= sq0;
  38.         q1 <= sq1;
  39.        
  40.     END Arc;
  41. -----------------------------------------------------------------------------------
  42.  
  43. -- FFT.vhd
  44. -----------------------------------------------------------------------------------
  45. LIBRARY IEEE;
  46. USE IEEE.STD_LOGIC_1164.ALL;
  47.  
  48. ENTITY FFT IS
  49.     PORT(
  50.         clk: IN STD_LOGIC;
  51.         q: OUT STD_LOGIC
  52.     );
  53. END FFT;
  54.  
  55. ARCHITECTURE Arc OF FFT IS
  56.     SIGNAL sq: STD_LOGIC;
  57.     BEGIN
  58.         PROCESS(clk)
  59.             BEGIN
  60.                 IF(clk'event AND clk='1') THEN -- clk'event: é o evento de subida/descida.
  61.                     q <= (not sq);
  62.                 END IF;
  63.             END PROCESS;
  64.     END Arc;
  65. -----------------------------------------------------------------------------------
  66.  
  67. -- Mux2x1.vhd
  68. -----------------------------------------------------------------------------------
  69. LIBRARY IEEE;
  70. USE IEEE.STD_LOGIC_1164.ALL;
  71.  
  72. ENTITY Mux2x1 IS
  73.     PORT(
  74.         a, b: IN STD_LOGIC;
  75.         sel: IN STD_LOGIC;
  76.         x: OUT STD_LOGIC
  77.     );
  78. END Mux2x1;
  79.  
  80. ARCHITECTURE arc OF Mux2x1 IS
  81.     BEGIN  
  82.         PROCESS(a,b,sel)
  83.             BEGIN
  84.                 IF(sel = '0') THEN
  85.                     x <= a;
  86.                 ELSE
  87.                     x <= b;
  88.                 END IF;
  89.         END PROCESS;
  90.     END arc;
  91.  
  92. -----------------------------------------------------------------------------------
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