library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_unsigned.ALL;

entity UART_TX is
    Port (clk9600: in std_logic;    -- 9600 Hz clock
            TX : out std_logic      -- TX pin
    );
end UART_TX;

architecture Behavioral of UART_TX is
-- dummy data
-- idle (1) for a 3 cycles, start bit (1 to 0 transition), 8 bits of data ('A'), stop bit (=1)
constant bits_to_transmit : std_logic_vector (0 to 12) := "1110100000101";
signal current_bit : std_logic :='1';
signal current_index: integer := 0; -- RTL shows that this is 32 bit number

begin
    process (clk9600) -- on every clock tick
    begin
        if rising_edge(clk9600) then
            -- grab the current bit (in first iteration current_index = 0)
            current_bit <= bits_to_transmit(current_index);
            -- increment index by one, check for overflow
            if current_index < 12 then
                current_index <= current_index + 1;
            else
                current_index <= 0;
            end if;
        end if;
    end process;
    -- assign TX the current bit
    TX <= current_bit;
end Behavioral;