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Jan 18th, 2020
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VHDL 0.52 KB | None | 0 0
  1. entity simu is
  2. port (in1: in integer;
  3.       in2: in integer;
  4.       in3: in integer;
  5.      out1: out integer;
  6.      out2: out integer;
  7.       clk: in bit);
  8. architecture arch of simu is
  9.     signal s1, s2, s3, s4, s5, s6, s7, s8: integer;
  10.     const M: integer := 10;
  11.     const C1: integer:= 89;
  12. begin
  13.     SUM: s1 <= in1+in2;
  14.     G1: s3 <= in2*(-980)/M;
  15.     G2: s2 <= C1*1/M; //tuka ne trqbva li M^2 da se deli shtoto i dvete sa mashtabirani?
  16.     D: process(in3, clk):
  17.         begin
  18.         if (clk'event AND clk='1') then
  19.         s6 <= in3;
  20.         end if
  21.        end process
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