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counterH

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Jun 27th, 2018
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4. use ieee.std_logic_unsigned.all;
  5.  
  6. entity counterH is Generic(
  7.     count_width : natural := 3
  8. );
  9. port(
  10.     clk: in std_logic;
  11.     reset: in std_logic;
  12.     count_enable: in std_logic;
  13.     count: out std_logic_vector(count_width-1 downto 0)
  14. );
  15. end counterH;
  16.  
  17. architecture arch of counterH is
  18.     signal temp_count : std_logic_vector(count_width-1 downto 0);
  19. begin
  20.  
  21. process(clk)
  22.     begin
  23.     if(rising_edge(clk)) then
  24.         if(reset = '1') then
  25.             temp_count <= (others => '0');
  26.         elsif (count_enable = '1') then
  27.             temp_count <= temp_count + 1;
  28.         end if;
  29.     end if;
  30. end process;
  31.  
  32. count <= temp_count;
  33.  
  34. end arch;
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