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voik3

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Jun 26th, 2019
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VHDL 0.39 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4.  
  5.  
  6. entity demultiplekser is
  7.     Port ( wej : in   STD_LOGIC_vector(1 downto 0);
  8.            wyj : out  STD_LOGIC_vector(3 downto 0));
  9. end demultiplekser;
  10.  
  11. architecture Behavioral of demultiplekser is
  12.  
  13. begin
  14. with wej select
  15. wyj <= "1110" when "00",
  16.          "1101" when "01",
  17.          "1011" when "10",
  18.          "0111" when others;
  19.  
  20. end Behavioral;
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