library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adc5bit is
    Port ( enable : in STD_LOGIC;
        comp : in STD_LOGIC;
        clock : in STD_LOGIC;
        reset : in STD_LOGIC;
        sA : out STD_LOGIC;
        sB : out STD_LOGIC;
        s1 : out STD_LOGIC;
        s2 : out STD_LOGIC;
        s3 : out STD_LOGIC;
        s4 : out STD_LOGIC;
        s5 : out STD_LOGIC;
        s6 : out STD_LOGIC;
        eoc : out STD_LOGIC;
        sh : out STD_LOGIC);
end adc5bit;

architecture Behavioral of adc5bit is
    type statetype is (state0, state1, state2, state3, state4, state5, state6);
    signal state : statetype;
    begin
        process (clock,reset,enable)
    begin
        if reset = '1' then
            state <= state0;
            sA <= '1';
            sB <= '1';
            s1 <= '1';
            s2 <= '1';
            s3 <= '1';
            s4 <= '1';
            s5 <= '1';
            s6 <= '1';
            sh <= '0';
            eoc <= '0';
        elsif (clock'event and clock='1' and enable='1') then
            case state is
            when state0 => state <= state1;
                sA <= '1';
                sB <= '1';
                s1 <= '1';
                s2 <= '1';
                s3 <= '1';
                s4 <= '1';
                s5 <= '1';
                s6 <= '1';
                sh <= '1';
                eoc <= '0';
            when state1 => state <= state2;
                sA <= '0';
                sB <= '0';
                s1 <= '1';
                s2 <= '0';
                s3 <= '0';
                s4 <= '0';
                s5 <= '0';
                s6 <= '0';
                sh <= '0';
            when state2 => state <= state3;
                if comp='1' then
                    s1 <='0';
                    s2 <='1';
                elsif comp='0' then
                    s2 <='1';
                end if;
            when state3 => state <= state4;
                if comp='1' then
                    s2 <='0';
                    s3 <='1';
                elsif comp='0' then
                    s3 <='1';
                end if;
            when state4 => state <= state5;
                if comp='1' then
                    s3 <='0';
                    s4 <='1';
                elsif comp='0' then
                    s4 <='1';
                end if;
            when state5 => state <= state6;
                if comp='1' then
                    s4 <='0';
                    s5 <='1';
                elsif comp='0' then
                    s5 <='1';
                end if;
            when state6 => state <= state0;
                if comp='1' then
                    s5 <='0';
                elsif comp='0' then
                    s5 <='1';
                end if;
                    eoc <= '1';
            end case;
        end if;
            if enable = '0' then
                sA <= '1';
                sB <= '1';
                s1 <= '1';
                s2 <= '1';
                s3 <= '1';
                s4 <= '1';
                s5 <= '1';
                s6 <= '1';
                sh <= '0';
                eoc <= '0';
            end if;
        end process;
end Behavioral;