FF T

library IEEE;

use IEEE.std_logic_1164.all;

entity FF_T is
port (
    T : IN  std_logic;
    Q : OUT std_logic);
end FF_T;

architecture architecture_FF_T of FF_T is

begin

    process (T) begin
    if rising_edge(T) then
        Q<= not Q;
    end if;
    end process;

end architecture_FF_T;