library ieee;
use ieee.std_logic_1164.all;

entity versuch01 is
  port(
    x1: in std_ulogic;
    x2: in std_ulogic;
    x3: in std_ulogic;
    x4: in std_ulogic;
    y1: out std_ulogic;
    y2: out std_ulogic
  );
end versuch01;

architecture versuch01_arch of versuch01 is
begin
  process
    begin
      y1 <= (x1 and not x4) or (not x1 and x2) or (not x1 and x3 and x4);
      y2 <= (not x1 or not x4) and (x1 or x4) and (x1 or x2 or x3);
    wait;
  end process;
end versuch01_arch;