--
-- VHDL Architecture Lab5VHDL_lib.Lab5VHDL_tester.tb
--
-- Created:
--          by - stud.stud (mmf417-8)
--          at - 18:38:40 05/15/19
--
-- using Mentor Graphics HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY Lab5VHDL_tester IS
   PORT(
      dataOut : IN     std_logic_vector (2 DOWNTO 0);
      clk     : OUT    std_logic;
      dataIn  : OUT    std_logic_vector (2 DOWNTO 0);
      rst     : OUT    std_logic
   );

-- Declarations

END Lab5VHDL_tester ;

--
ARCHITECTURE tb OF Lab5VHDL_tester IS
BEGIN

END ARCHITECTURE tb;