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MAC dodatak, za direktnu, last section

Jun 26th, 2018
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VHDL 0.58 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. use IEEE.NUMERIC_STD.ALL;
  5.  
  6. entity mac_last is
  7.     generic (input_data_width : natural :=12);
  8.     Port ( u_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
  9.            b_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
  10.            mac_i : in STD_LOGIC_VECTOR (2*input_data_width-1 downto 0);
  11.            mac_o : out STD_LOGIC_VECTOR (2*input_data_width-1 downto 0));
  12. end mac_last;
  13.  
  14. architecture Behavioral of mac_last is
  15.  
  16. begin
  17.    
  18.     mac_o <= std_logic_vector(signed(mac_i) + (signed(u_i) * signed(b_i)));
  19.  
  20. end Behavioral;
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