library ieee;
use IEEE.Std_Logic_1164.all;


entity tb_Config is
end tb_Config;

entity secondDevice is
end secondDevice;

architecture TEST of tb_Config is

  component secondDevice
  port(D : in std_logic;
       S, R, CLK: in std_logic;
       Q: inout std_logic_vector ( 3 downto 0)
    );
  end component;

signal in_D, in_S, in_R, in_CLK: std_logic := '0';
signal out_Q_BEH, out_Q_STR, out_Q_RTL : std_logic_vector ( 3 downto 0);

begin

p1 : secondDevice port map(in_D, in_S, in_R, in_CLK, out_Q_BEH);
p2 : secondDevice port map(in_D, in_S, in_R, in_CLK, out_Q_STR);
p3 : secondDevice port map(in_D, in_S, in_R, in_CLK, out_Q_RTL);
p4 : process
     begin
       in_D <= not in_D;
       wait for 75 ns;
     end process;
p5 : process
     begin
       wait for 100 ns;
       in_S <= not in_S;
       wait for 20 ns;
       in_S <= not in_S;
       wait for 100 ns;
     end process;
p6 : process
     begin
       wait for 180 ns;
       in_R <= not in_R;
       wait for 20 ns;
       in_R <= not in_R;
       wait for 100 ns;
     end process;
p7 : process
     begin
       wait for 7 ns;
       in_CLK <= not in_CLK;
     end process;
end TEST;


library en41_belous_lab2;
use en41_belous_lab2.all;
configuration config1 of tb_Config is
 for TEST
 for p1 : secondDevice use entity en41_belous_lab2.secondDevice_RTL(RTL); end for;
 for p2 : secondDevice use entity en41_belous_lab2.secondDevice_BEH(BEH); end for;
 for p3 : secondDevice use entity en41_belous_lab2.secondDevice_STR(STR); end for;
 end for;
end configuration;