library ieee;
use ieee.std_logic_1164.all;

entity versuch01b is
  port(
    x: in std_logic_vector (3 downto 0);
    y: out std_logic_vector (3 downto 0)
  );
end versuch01b;

architecture versuch01b_arch of versuch01b is
begin
  funktionstabelle: process(x)
  begin
    case x is
      when "0000"|"0001"|"0010"|"1011"|"1101"|"1111" => y <= "0";
      when "0011"|"0101"|"0111"|"1000"|"1010"|"1100"|"1110" => y <= "1";
      --when "0100"|"0110"|"1001" => y <= "0";
      when others => null;
    end case;
  end process funktionstabelle;
end versuch01b_arch;