--------------------------------
--- Full Adder in 4 stages
-- Pipelined
-- Clock Cycles
--- Dr. Amoo
--- 10/25/2017
--------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
--USE IEEE.std_logic_unsigned.all;
----USE IEEE.NUMERIC_STD.all;
ENTITY JOSEPH_4_STAGE_ADDER IS
 GENERIC(P: integer:= 16;

W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_B :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_Q :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_F :OUT STD_LOGIC_VECTOR(W-2 DOWNTO 0)
 );
END JOSEPH_4_STAGE_ADDER;

ARCHITECTURE STRUCTURAL OF JOSEPH_4_STAGE_ADDER IS
COMPONENT JOSEPH_First_BSlice
PORT (
Op_A :IN STD_LOGIC;
Op_B :IN STD_LOGIC;
SUM_Q :OUT STD_LOGIC;
Carry_Q :OUT STD_LOGIC
 );
END COMPONENT;
COMPONENT JOSEPH_FA_BSlice
PORT (
Op_A :IN STD_LOGIC;
Op_B :IN STD_LOGIC;
Op_C :IN STD_LOGIC;
SUM_Q :OUT STD_LOGIC;
Carry_Q :OUT STD_LOGIC
 );
END COMPONENT;


COMPONENT REG_FA
 GENERIC(P: integer:= 16;
 W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_B :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_Sum :IN STD_LOGIC_VECTOR(W-1 DOWNTO 0); -- sum
Op_Carry:IN STD_LOGIC; -- carry
Op_AQ :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_BQ :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_SQ :OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
Op_C :OUT STD_LOGIC
 );
END COMPONENT;


COMPONENT REG_FA_lastslice
 GENERIC(P: integer:= 16;
 W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC; -- sign bit
Op_B :IN STD_LOGIC; -- sign bit
Op_Sum :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0); -- sum
Op_Carry:IN STD_LOGIC; -- carry
Op_Q :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_F :OUT STD_LOGIC_VECTOR(W-2 DOWNTO 0)
 );
END COMPONENT;

SIGNAL S_A1: STD_LOGIC_VECTOR(3*W-1 DOWNTO 0);
SIGNAL S_A2: STD_LOGIC_VECTOR(2*W-1 DOWNTO 0);
SIGNAL S_A3: STD_LOGIC_VECTOR(1*W-1 DOWNTO 0);
SIGNAL S_B1: STD_LOGIC_VECTOR(3*W-1 DOWNTO 0);
SIGNAL S_B2: STD_LOGIC_VECTOR(2*W-1 DOWNTO 0);
SIGNAL S_B3: STD_LOGIC_VECTOR(1*W-1 DOWNTO 0);
SIGNAL My_SUM_Q1: STD_LOGIC_VECTOR(W-1 DOWNTO 0);
SIGNAL My_SUM_Q2: STD_LOGIC_VECTOR(2*W-1 DOWNTO 0);
SIGNAL My_SUM_Q3: STD_LOGIC_VECTOR(3*W-1 DOWNTO 0);
SIGNAL My_SUM_Q4: STD_LOGIC_VECTOR(4*W-1 DOWNTO 0);
SIGNAL SOP_C1: STD_LOGIC;
SIGNAL SOP_C2: STD_LOGIC;
SIGNAL SOP_C3: STD_LOGIC;
SIGNAL SOP_C4: STD_LOGIC;
SIGNAL SOP_C5: STD_LOGIC;
SIGNAL SOP_C6: STD_LOGIC;
SIGNAL SOP_C7: STD_LOGIC;
SIGNAL SOP_C8: STD_LOGIC;
SIGNAL SOP_C9: STD_LOGIC;
SIGNAL SOP_C10: STD_LOGIC;
SIGNAL SOP_C11: STD_LOGIC;
SIGNAL SOP_C12: STD_LOGIC;
SIGNAL SOP_C13: STD_LOGIC;
SIGNAL SOP_C14: STD_LOGIC;
SIGNAL SOP_C15: STD_LOGIC;
SIGNAL SOP_C16: STD_LOGIC;
SIGNAL SOP_C17: STD_LOGIC;
SIGNAL SOP_C18: STD_LOGIC;
SIGNAL SOP_C19: STD_LOGIC;



BEGIN
----------------------------------------------------
-- 1st STAGE: 4-Bit Add
----------------------------------------------------
A1: JOSEPH_First_BSlice
PORT MAP(Op_A(W-4), Op_B(W-4), My_SUM_Q1(W-4),SOP_C1);
A2: JOSEPH_FA_BSlice
PORT MAP(Op_A(W-3), Op_B(W-3), SOP_C1, My_SUM_Q1(W-3), SOP_C2);
A3: JOSEPH_FA_BSlice
PORT MAP(Op_A(W-2), Op_B(W-2), SOP_C2, My_SUM_Q1(W-2), SOP_C3);
A4: JOSEPH_FA_BSlice
PORT MAP(Op_A(W-1), Op_B(W-1), SOP_C3, My_SUM_Q1(W-1), SOP_C4);
A5: REG_FA GENERIC MAP(P-W, W, E)
PORT MAP(Clk, Reset, En, Op_A(P-1 DOWNTO W), Op_B(P-1 DOWNTO
W),My_SUM_Q1, SOP_C4, S_A1, S_B1, My_SUM_Q2(W-1 DOWNTO 0), SOP_C5);



----------------------------------------------------
-- 2nd STAGE: 4-Bit Add
----------------------------------------------------
B1: JOSEPH_FA_BSlice
PORT MAP(S_A1(W-4), S_B1(W-4), SOP_C5, My_SUM_Q2(2*W-4),SOP_C6);
B2: JOSEPH_FA_BSlice
PORT MAP(S_A1(W-3), S_B1(W-3), SOP_C6, My_SUM_Q2(2*W-3), SOP_C7);
B3: JOSEPH_FA_BSlice
PORT MAP(S_A1(W-2), S_B1(W-2), SOP_C7, My_SUM_Q2(2*W-2), SOP_C8);
B4: JOSEPH_FA_BSlice
PORT MAP(S_A1(W-1), S_B1(W-1), SOP_C8, My_SUM_Q2(2*W-1), SOP_C9);
B5: REG_FA GENERIC MAP(P-2*W, 2*W, E)
PORT MAP(Clk, Reset, En, S_A1(3*W-1 DOWNTO W), S_B1(3*W-1 DOWNTO
W),My_SUM_Q2, SOP_C9, S_A2, S_B2, My_SUM_Q3(2*W-1 DOWNTO 0), SOP_C10);

----------------------------------------------------
-- 3rd STAGE: 4-Bit Add
----------------------------------------------------
C1: JOSEPH_FA_BSlice
PORT MAP(S_A2(W-4), S_B2(W-4), SOP_C10, My_SUM_Q3(3*W-4), SOP_C11);
C2: JOSEPH_FA_BSlice
PORT MAP(S_A2(W-3), S_B2(W-3), SOP_C11, My_SUM_Q3(3*W-3), SOP_C12);
C3: JOSEPH_FA_BSlice
PORT MAP(S_A2(W-2), S_B2(W-2), SOP_C12, My_SUM_Q3(3*W-2), SOP_C13);
C4: JOSEPH_FA_BSlice
PORT MAP(S_A2(W-1), S_B2(W-1), SOP_C13, My_SUM_Q3(3*W-1), SOP_C14);
C5: REG_FA GENERIC MAP(P-3*W, 3*W, E)
PORT MAP(Clk, Reset, En, S_A2(2*W-1 DOWNTO W), S_B2(2*W-1 DOWNTO
W),My_SUM_Q3, SOP_C14, S_A3, S_B3, My_SUM_Q4(3*W-1 DOWNTO 0), SOP_C15);

----------------------------------------------------
-- 4rd STAGE: 4-Bit Add
----------------------------------------------------
D1: JOSEPH_FA_BSlice
PORT MAP(S_A3(W-4), S_B3(W-4), SOP_C15, My_SUM_Q4(4*W-4), SOP_C16);
D2: JOSEPH_FA_BSlice
PORT MAP(S_A3(W-3), S_B3(W-3), SOP_C16, My_SUM_Q4(4*W-3), SOP_C17);
D3: JOSEPH_FA_BSlice
PORT MAP(S_A3(W-2), S_B3(W-2), SOP_C17, My_SUM_Q4(4*W-2), SOP_C18);
D4: JOSEPH_FA_BSlice
PORT MAP(S_A3(W-1), S_B3(W-1), SOP_C18, My_SUM_Q4(4*W-1), SOP_C19);
D5: REG_FA_lastslice GENERIC MAP(P, W, E)
PORT MAP(Clk, Reset, En, S_A3(W-1), S_B3(W-1),My_SUM_Q4, My_SUM_Q4(P-1), OP_Q,
OP_F);
END STRUCTURAL;