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- library ieee; -- Load the ieee 1164 library
- use ieee.std_logic_1164.all; -- Make the package 'visible'
- -- The top level entity of the test bench has no ports...
- entity adder4bit_slow_tb is
- end adder4bit_slow_tb;
- architecture stimulus of adder4bit_slow_tb is
- -- First, declare the lower-level entity...
- component adder4bit_slow
- port(a ,b : in std_logic_vector(3 downto 0);
- c_in: in std_logic;
- s : out std_logic_vector(3 downto 0);
- c_out : out std_logic);
- end component;
- -- Next, declare some local signals to assign values to AN observe...
- -- adder4bit_slow input
- signal a ,b : std_logic_vector(3 downto 0);
- signal c_in : std_logic;
- -- adder4bit_slow outputss
- signal s : std_logic_vector(3 downto 0);
- signal c_out : std_logic;
- begin
- -- Create an instance of the component under test
- adder4bit_slow_instance: adder4bit_slow port map( a => a, b => b, c_in => c_in, s => s, c_out => c_out);
- -- Now define a process to apply some stimulus over time...
- process
- constant PERIOD: time := 40 ns;
- begin
- avector : for a4 in 0 to 15 loop
- if (a4 = 15) then
- a <= X"F";
- else if (a4 = 14) then
- a <= X"E";
- else if (a4 = 13) then
- a <= X"D";
- else if (a4 = 12) then
- a <= X"C";
- else if (a4 = 11) then
- a <= X"B";
- else if (a4 = 10) then
- a <= X"A";
- else if (a4 = 9) then
- a <= X"9";
- else if (a4 = 8) then
- a <= X"8";
- else if (a4 = 7) then
- a <= X"7";
- else if (a4 = 6) then
- a <= X"6";
- else if (a4 = 5) then
- a <= X"5";
- else if (a4 = 4) then
- a <= X"4";
- else if (a4 = 3) then
- a <= X"3";
- else if (a4 = 2) then
- a <= X"2";
- else if (a4 = 1) then
- a <= X"1";
- else if (a4 = 0) then
- a <= X"0";
- end if;
- wait for PERIOD;
- end loop avector;
- -- put breakpoint to line below
- wait for PERIOD;
- -- do not run again
- wait;
- end process;
- end stimulus;
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