Orion-128 main body

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity orion is
    port (
        CLOCK_50        : in  std_logic;

        SW              : in std_logic_vector(9 downto 0);
        KEY         : in std_logic_vector(3 downto 0);

        LEDR            : out std_logic_vector(9 downto 0);

        HEX0            : out std_logic_vector(6 downto 0);
        HEX1            : out std_logic_vector(6 downto 0);
        HEX2            : out std_logic_vector(6 downto 0);
        HEX3            : out std_logic_vector(6 downto 0);
        HEX4            : out std_logic_vector(6 downto 0);
        HEX5            : out std_logic_vector(6 downto 0);

        VGA_R           : out std_logic_vector(7 downto 0);
        VGA_G           : out std_logic_vector(7 downto 0);
        VGA_B           : out std_logic_vector(7 downto 0);
        VGA_BLANK_N : out std_logic;
        VGA_CLK     : out std_logic;
        VGA_HS      : out std_logic;
        VGA_SYNC_N  : out std_logic;
        VGA_VS      : out std_logic
    );
end entity;

architecture rtl of orion is

    component orion_pll is
        port (
            refclk   : in  std_logic := 'X'; -- clk
            rst      : in  std_logic := 'X'; -- reset
            outclk_0 : out std_logic;        -- clk 10MHz
            outclk_1 : out std_logic         -- clk 100MHz
        );
    end component orion_pll;

    component pll is
        port (
            refclk   : in  std_logic := 'X'; -- clk
            rst      : in  std_logic := 'X'; -- reset
            outclk_0 : out std_logic         -- clk 148.5MHz
        );
    end component pll;

    component vga
    port
    (
        clk     :    in std_logic;
        clk_10  :    in std_logic;

        /*SSI       :    in std_logic;
        KSI     :    in std_logic;
        R           :    in std_logic;
        G           :    in std_logic;
        B           :    in std_logic;
        I           :    in std_logic;*/
        vaddr       :    in std_logic_vector(15 downto 0);
        vdata       :    in std_logic_vector(15 downto 0);

        reset_n :    in std_logic;

        vga_r       :    out std_logic_vector(7 downto 0);
        vga_g       :    out std_logic_vector(7 downto 0);
        vga_b       :    out std_logic_vector(7 downto 0);
        hsync       :    out std_logic;
        vsync       :    out std_logic;
        blank_n :    out std_logic
    );
    end component;

    component debounce
        generic (
            WIDTH : INTEGER := 14;
            POLARITY : STRING := "HIGH";
            TIMEOUT : INTEGER := 50000;
            TIMEOUT_WIDTH : INTEGER := 20
        );
        port
        (
            clk     :   in std_logic;
            reset_n :   in std_logic;
            data_in :   in std_logic_vector(WIDTH-1 downto 0);
            data_out    :   out std_logic_vector(WIDTH-1 downto 0)
        );
    end component;

    component hex_led
        port (
            clk     : in    std_logic;
            reset_n : in    std_logic;
            hex_code    : in    std_logic_vector(3 downto 0);
            hex_led : out   std_logic_vector(6 downto 0)
        );
    end component;

    component vm80a
        port
        (
            pin_clk     :    in std_logic;
            pin_f1      :    in std_logic;
            pin_f2      :    in std_logic;
            pin_reset   :    in std_logic;
            pin_a           :    out std_logic_vector(15 downto 0);
            pin_d           :    inout std_logic_vector(7 downto 0);
            pin_hold        :    in std_logic;
            pin_hlda        :    out std_logic;
            pin_ready   :    IN std_logic;
            pin_wait        :    out std_logic;
            pin_int     :    in std_logic;
            pin_inte        :    out std_logic;
            pin_sync        :    out std_logic;
            pin_dbin        :    out std_logic;
            pin_wr_n        :    out std_logic
        );
    end component;

    component rom_base
        port
        (
            address : in  std_logic_vector(10 downto 0);
            clock       : in  std_logic;
            rden        : in  std_logic;
            q           : out std_logic_vector(7 downto 0)
        );
    end component;

    component ram_base
        port
        (
            address : in  std_logic_vector(15 downto 0);
            clock       : in  std_logic;
            data        : in std_logic_vector(7 downto 0);
            wren        : in  std_logic;
            q           : out std_logic_vector(7 downto 0)
        );
    end component;

--------------------------------------------------------------------------------
--                          ГЛОБАЛЬНЫЕ СИГНАЛЫ                                --
--------------------------------------------------------------------------------
signal clk_50MHz            : std_logic;
signal clk_10MHz            : std_logic;
signal clk_100MHz           : std_logic;
signal clk_148_5MHz     : std_logic;

signal debounced            : std_logic_vector(13 downto 0);
signal KEY_debounced        : std_logic_vector(3 downto 0);
signal SW_debounced     : std_logic_vector(9 downto 0);

--------------------------------------------------------------------------------
--                  СИГНАЛЫ ДЛЯ ФОРМИРОВАНИЯ ВИДЕОСИГНАЛА                     --
--------------------------------------------------------------------------------
signal vram_read            : std_logic;                            -- переключение адресации памяти на видео
signal vram_addr            : std_logic_vector(15 downto 0);    -- адрес для чтения из видеопамяти
signal vram_nib_addr        : std_logic_vector(15 downto 0);
signal vram_buf00           : std_logic_vector( 7 downto 0); -- данные, прочитанные из 0-ого банка
signal vram_buf01           : std_logic_vector( 7 downto 0); -- данные, прочитанные из 1-ого банка
signal vram_buf10           : std_logic_vector( 7 downto 0);
signal vram_buf11           : std_logic_vector( 7 downto 0);
signal vram_data            : std_logic_vector(15 downto 0);    -- преобразованные пиксели (4 пикселя)
signal vram_bank_idx        : std_logic_vector( 1 downto 0); -- номер банка памяти
signal vram_bank_idx_tmp: std_logic_vector( 1 downto 0) := "11";


signal video_frame_end  : std_logic;

constant VIDEO_PXL_IN_LINE      : std_logic_vector(8 downto 0) := 9X"17f";  -- 384 пикселя в строке
constant VIDEO_LINE_IN_FRAME    : std_logic_vector(8 downto 0) := 9X"ff";       -- 256 строк в кадре

--------------------------------------------------------------------------------
--                             СИГНАЛЫ ПАМЯТИ                                 --
--------------------------------------------------------------------------------
signal ram_addr         : std_logic_vector(15 downto 0);
signal ram_we0_n            : std_logic;
signal ram_re0_n            : std_logic;
signal ram_data_wr0     : std_logic_vector( 7 downto 0);
signal ram_data_rd0     : std_logic_vector( 7 downto 0);
signal ram_we1_n            : std_logic;
signal ram_re1_n            : std_logic;
signal ram_data_wr1     : std_logic_vector( 7 downto 0);
signal ram_data_rd1     : std_logic_vector( 7 downto 0);


signal clk_F1               : std_logic;
signal clk_F2               : std_logic;

--------------------------------------------------------------------------------
--                         ВНЕШНИЕ СИГНАЛЫ ОРИОНА                             --
--------------------------------------------------------------------------------
signal or_reset_btn     : std_logic;
signal or_ready         : std_logic := '1';

--------------------------------------------------------------------------------
--                       ВНУТРЕННИЕ СИГНАЛЫ ОРИОНА                            --
--------------------------------------------------------------------------------
signal clock_cnt_0      : std_logic_vector(8 downto 0) := 9X"0";
signal clock_ovf_0      : std_logic;
signal clock_cnt_1      : std_logic_vector(8 downto 0) := 9X"0";

signal reset_p              : std_logic;
signal reset_n              : std_logic;
signal cpu_ready            : std_logic;
signal cpu_int              : std_logic;
signal cpu_int_n            : std_logic;
signal cpu_inte         : std_logic;
signal cpu_inte_n           : std_logic;
signal cpu_sync         : std_logic;
signal cpu_hlda         : std_logic := '0';
signal cpu_rd               : std_logic;
signal cpu_rd_n         : std_logic;
signal cpu_wr               : std_logic;
signal cpu_wr_n         : std_logic;
signal bus_addr         : std_logic_vector(17 downto 0);
signal bus_data         : std_logic_vector( 7 downto 0);

signal addr_FXXX            : std_logic;
signal addr_F4XX            : std_logic;
signal addr_F8XX            : std_logic;

signal dsyn_p               : std_logic;
signal dsyn_n               : std_logic;

signal rom_re               : std_logic;
signal rom_data         : std_logic_vector( 7 downto 0);

signal port_F800            : std_logic_vector(3 downto 0); -- управление цветом
signal port_F900            : std_logic_vector(1 downto 0); -- управление страницами памяти
signal port_FA00            : std_logic_vector(1 downto 0); -- управление экранными облястями
--signal port_FB00          : std_logic_vector(2 downto 0); -- резерв

signal mem_addr         : std_logic_vector(15 downto 0);
signal mem_addr_hi      : std_logic_vector( 1 downto 0);
signal mem_wdata0           : std_logic_vector( 7 downto 0);
signal mem_rdata0           : std_logic_vector( 7 downto 0);
signal mem_wdata1           : std_logic_vector( 7 downto 0);
signal mem_rdata1           : std_logic_vector( 7 downto 0);
signal mem_wdata2           : std_logic_vector( 7 downto 0);
signal mem_rdata2           : std_logic_vector( 7 downto 0);
signal mem_wdata3           : std_logic_vector( 7 downto 0);
signal mem_rdata3           : std_logic_vector( 7 downto 0);
signal mem_we               : std_logic;
signal mem_we_bank      : std_logic;
signal mem_we_bank_0        : std_logic;
signal mem_we_bank_1        : std_logic;
signal mem_we_bank_2        : std_logic;
signal mem_we_bank_3        : std_logic;
signal mem_cs_bank      : std_logic;
signal mem_cs_bank_0        : std_logic;
signal mem_cs_bank_1        : std_logic;
signal mem_cs_bank_2        : std_logic;
signal mem_cs_bank_3        : std_logic;

signal sel_CSROM            : std_logic;
signal sel_CSROM_n      : std_logic;
signal sel_port_F4XX        : std_logic;
signal sel_port_F400        : std_logic;
signal sel_port_F500        : std_logic;
signal sel_port_F600        : std_logic;
signal sel_port_F700        : std_logic;
signal sel_port_F8XX        : std_logic;
signal sel_port_F800        : std_logic;
signal sel_port_F900        : std_logic;
signal sel_port_FA00        : std_logic;
signal sel_port_FB00        : std_logic;

begin
--------------------------------------------------------------------------------
--                       СВЯЗЬ СИГНАЛОВ С ПИНАМИ МС                           --
--------------------------------------------------------------------------------
clk_50MHz <= CLOCK_50;
or_reset_btn <= KEY_debounced(0);
LEDR(0) <= clk_10MHz;
LEDR(1) <= clk_F1;
LEDR(2) <= clk_F2;
LEDR(3) <= '0';
LEDR(4) <= '0';
LEDR(5) <= '0';
LEDR(6) <= '0';
LEDR(7) <= '0';
LEDR(8) <= '0';
LEDR(9) <= '0';

cpu_int <= not cpu_int_n;
cpu_inte_n <= not cpu_inte;
cpu_wr <= not cpu_wr_n;
cpu_rd_n <= cpu_rd;

--------------------------------------------------------------------------------
--                      ПОДКЛЮЧЕНИЕ ВНЕШНИХ МОДУЛЕЙ                           --
--------------------------------------------------------------------------------
-- основной PLL
pll_orion: orion_pll
    port map (
        clk_50MHz,
        '0',
        clk_10MHz,
        clk_100MHz
    );

-- PLL для видеовыхода
pll_vga: pll
    port map (
        clk_50MHz,
        '0',
        clk_148_5MHz
    );

-- фильтр дребезга контактов
deb: debounce
    port map (
        clk_10MHz,
        '1',
        KEY & SW,
        debounced
    );
KEY_debounced <= debounced(13 downto 10);
SW_debounced  <= debounced(9 downto 0);

h0: hex_led
    port map (
        clk_10MHz,
        reset_n,
        bus_addr(3 downto 0),
        HEX0
    );

h1: hex_led
    port map (
        clk_10MHz,
        reset_n,
        bus_addr(7 downto 4),
        HEX1
    );

h2: hex_led
    port map (
        clk_10MHz,
        reset_n,
        bus_addr(11 downto 8),
        HEX2
    );

h3: hex_led
    port map (
        clk_10MHz,
        reset_n,
        bus_addr(15 downto 12),
        HEX3
    );

h4: hex_led
    port map (
        clk_10MHz,
        reset_n,
        bus_data(3 downto 0),
        HEX4
    );

h5: hex_led
    port map (
        clk_10MHz,
        reset_n,
        bus_data(7 downto 4),
        HEX5
    );

video: vga
    port map (
        clk_148_5MHz,
        clk_10MHz,

        vram_nib_addr,
        vram_data,

        reset_n,

        VGA_R,
        VGA_G,
        VGA_B,
        VGA_HS,
        VGA_VS,
        VGA_BLANK_N
    );

VGA_SYNC_N <= '0';
VGA_CLK <= clk_148_5MHz;

cpu: vm80a
    port map (
        pin_clk     => clk_10MHz,
        pin_f1      => clk_F1,
        pin_f2      => clk_F2,
        pin_reset   => reset_p,
        pin_a           => bus_addr(15 downto 0),
        pin_d           => bus_data,
        pin_hold        => '0',
        pin_hlda        => cpu_hlda,
        pin_ready   => cpu_ready,
        pin_int     => cpu_int,
        pin_inte        => cpu_inte,
        pin_sync        => cpu_sync,
        pin_dbin        => cpu_rd,
        pin_wr_n        => cpu_wr_n
    );

rom: rom_base
    port map (
        bus_addr(10 downto 0),
        clk_10MHz,
        rom_re,
        rom_data
    );
rom_re <= sel_CSROM and cpu_rd;
bus_data <= rom_data when (rom_re = '1')
    else (others => 'Z');

ram0: ram_base
    port map
    (
        mem_addr,
        clk_10MHz,
        mem_wdata0,
        mem_we_bank_0,
        mem_rdata0
    );
mem_wdata0 <= bus_data when ((mem_cs_bank_0 = '1') and (cpu_rd = '0'))
            else (others => 'Z');
bus_data <= mem_rdata0 when ((mem_cs_bank_0 = '1') and (cpu_rd = '1'))
            else (others => 'Z');

ram1: ram_base
    port map
    (
        mem_addr,
        clk_10MHz,
        mem_wdata1,
        mem_we_bank_1,
        mem_rdata1
    );
mem_wdata1 <= bus_data when ((mem_cs_bank_1 = '1') and (cpu_rd = '0'))
            else (others => 'Z');
bus_data <= mem_rdata1 when ((mem_cs_bank_1 = '1') and (cpu_rd = '1'))
            else (others => 'Z');

--------------------------------------------------------------------------------
--                    ФОРМИРОВАНИЕ ТАКТОВЫХ СИГНАЛОВ                          --
--------------------------------------------------------------------------------

    process (clk_10MHz)
    begin
        if (rising_edge(clk_10MHz)) then
            if (clock_cnt_0 = VIDEO_PXL_IN_LINE) then
                clock_ovf_0 <= '1';
                clock_cnt_0 <= 9X"0";
            else
                clock_ovf_0 <= '0';
                clock_cnt_0 <= clock_cnt_0 + '1';
            end if;
        end if;
    end process;

clk_F1 <= (clock_cnt_0(0) and clock_cnt_0(1));
clk_F2 <= (not clock_cnt_0(1));

    process (clock_ovf_0)
    begin
        if (rising_edge(clock_ovf_0)) then
            if (clock_cnt_1 = VIDEO_LINE_IN_FRAME) then
                clock_cnt_1 <= 9X"0";
                video_frame_end <= '1';
            else
                clock_cnt_1 <= clock_cnt_1 + '1';
                video_frame_end <= '0';
            end if;
        end if;
    end process;

vram_nib_addr <= '0' & clock_cnt_1(7 downto 0) & clock_cnt_0(8 downto 2);
vram_addr <= vram_bank_idx & clock_cnt_0(8 downto 3) & clock_cnt_1(7 downto 0);

--------------------------------------------------------------------------------
--                      ФОРМИРОВАНИЕ ВИДЕО-СИГНАЛОВ                           --
--------------------------------------------------------------------------------

mem_addr <= vram_addr when (dsyn_p = '0')
    else bus_addr(15 downto 0);

    -- DD48, DD48 - занесение данных в первый буффер
    process (clk_10MHz)
    begin
        if (rising_edge(clk_10MHz)) then
            if (dsyn_p = '0') then
                --vram_buf00 <= mem_rdata0;
                vram_buf00 <= SW_debounced(9 downto 2);
                vram_buf01 <= mem_rdata1;
            end if;
        end if;
    end process;

    -- DD51, DD52 - занесение данных во 2-ой буффер
    process (clk_10MHz)
    begin
        if (rising_edge(clk_10MHz)) then
            if (clock_cnt_0(2 downto 0) = "111") then
                vram_buf10 <= vram_buf00;

                if (port_F800(2) = '0') then
                    vram_buf11 <= (others => '0');
                elsif (port_F800(1) = '0') then
                    vram_buf11 <= vram_buf01;
                end if;
            end if;
        end if;
    end process;

    -- формирование цветов для 4-х пикселей
vram_data(15) <= '0';   -- I
vram_data(14) <= '0';   -- B
vram_data(13) <= vram_buf10(7) when (clock_cnt_0(2) = '0')  -- G
                else vram_buf10(3);
vram_data(12) <= '0';   -- R
vram_data(11) <= '0';   -- I
vram_data(10) <= '0';   -- B
vram_data( 9) <= vram_buf10(6) when (clock_cnt_0(2) = '0')  -- G
                else vram_buf10(2);
vram_data( 8) <= '0';   -- R
vram_data( 7) <= '0';   -- I
vram_data( 6) <= '0';   -- B
vram_data( 5) <= vram_buf10(5) when (clock_cnt_0(2) = '0')  -- G
                else vram_buf10(1);
vram_data( 4) <= '0';   -- R
vram_data( 3) <= '0';   -- I
vram_data( 2) <= '0';   -- B
vram_data( 1) <= vram_buf10(4) when (clock_cnt_0(2) = '0')  -- G
                else vram_buf10(0);
vram_data( 0) <= '0';   -- R

--------------------------------------------------------------------------------
--                            ОБРАБОТКА ПОРТОВ                                --
--------------------------------------------------------------------------------

addr_FXXX <= bus_addr(12) and bus_addr(13) and bus_addr(14) and bus_addr(15);
addr_F4XX <= addr_FXXX and bus_addr(10);
addr_F8XX <= addr_FXXX and bus_addr(11);
sel_CSROM <= addr_F8XX or (not port_F800(3));

sel_CSROM_n      <= not sel_CSROM;

    -- DD18.1 - переключение страниц памяти
    process (clk_10MHz)
    begin
        if (rising_edge(clk_10MHz)) then
            if (sel_port_F900 = '1') then
                bus_addr(16) <= bus_data(0);
                bus_addr(17) <= bus_data(1);
            end if;
        end if;
    end process;

    -- DD18.2
    process (clk_10MHz)
    begin
        if (rising_edge(clk_10MHz)) then
            if (clk_F2 = '1') then
                reset_p <= not or_reset_btn;
                reset_n <= or_reset_btn;

                cpu_ready <= or_ready;
            end if;
        end if;
    end process;

    -- DD13.2
    process (clk_F2)
    begin
        if (rising_edge(clk_F2)) then
            dsyn_p <= cpu_sync;
            dsyn_n <= not cpu_sync;
        end if;
    end process;

    -- DD29 - управление банками памяти
mem_addr_hi(0) <= bus_addr(16) and (not addr_FXXX);
mem_addr_hi(1) <= bus_addr(17) and (not addr_FXXX);
mem_we <= clk_F2 and (not cpu_rd);
mem_cs_bank <= dsyn_p and sel_CSROM and (not addr_F4XX);
    mem_cs_bank_0 <= '1' when ((mem_addr_hi = "00") and (mem_cs_bank = '1'))
                    else '0';
    mem_cs_bank_1 <= '1' when ((mem_addr_hi = "01") and (mem_cs_bank = '1'))
                    else '0';
    mem_cs_bank_2 <= '1' when ((mem_addr_hi = "10") and (mem_cs_bank = '1'))
                    else '0';
    mem_cs_bank_3 <= '1' when ((mem_addr_hi = "11") and (mem_cs_bank = '1'))
                    else '0';
mem_we_bank <= dsyn_p and mem_we;
    mem_we_bank_0 <= '1' when ((mem_addr_hi = "00") and (mem_we_bank = '1'))
                    else '0';
    mem_we_bank_1 <= '1' when ((mem_addr_hi = "01") and (mem_we_bank = '1'))
                    else '0';
    mem_we_bank_2 <= '1' when ((mem_addr_hi = "10") and (mem_we_bank = '1'))
                    else '0';
    mem_we_bank_3 <= '1' when ((mem_addr_hi = "11") and (mem_we_bank = '1'))
                    else '0';

-- DD27 - дешифратор портов
sel_port_F4XX <= addr_F4XX and (not sel_CSROM);
    sel_port_F400 <= '1' when ((sel_port_F4XX = '1') and (bus_addr(9 downto 0) = "00"))
                    else '0';
    sel_port_F500 <= '1' when ((sel_port_F4XX = '1') and (bus_addr(9 downto 0) = "01"))
                    else '0';
    sel_port_F600 <= '1' when ((sel_port_F4XX = '1') and (bus_addr(9 downto 0) = "10"))
                    else '0';
    sel_port_F700 <= '1' when ((sel_port_F4XX = '1') and (bus_addr(9 downto 0) = "11"))
                    else '0';
sel_port_F8XX <= mem_we_bank_0 and sel_CSROM;
    sel_port_F800 <= '1' when ((sel_port_F8XX = '1') and (bus_addr(9 downto 0) = "00"))
                    else '0';
    sel_port_F900 <= '1' when ((sel_port_F8XX = '1') and (bus_addr(9 downto 0) = "01"))
                    else '0';
    sel_port_FA00 <= '1' when ((sel_port_F8XX = '1') and (bus_addr(9 downto 0) = "10"))
                    else '0';
    sel_port_FB00 <= '1' when ((sel_port_F8XX = '1') and (bus_addr(9 downto 0) = "11"))
                    else '0';

    -- DD28 - переключение экранных областей
    process (clk_10MHz)
    begin
        if (rising_edge(clk_10MHz)) then
            if (sel_port_FA00 = '1') then
                vram_bank_idx_tmp <= bus_data(1 downto 0);
            end if;

            if (video_frame_end = '1') then
                vram_bank_idx <= vram_bank_idx_tmp;
            end if;
        end if;
    end process;

    -- DD30 - управление цветом
    process (reset_n, sel_port_F800)
    begin
        if (reset_n = '0') then
            port_F800 <= "0000";
        elsif (rising_edge(sel_port_F800)) then
            port_F800 <= '1' & bus_data(2 downto 0);
        end if;
    end process;
end rtl;