SPI to databus AVR asm

    asm volatile(
      "ldi    __temp_reg__,1\n\t"
      "ldi    r20, 0\n\t"
      "ldi    r21, 0\n\t"

      // initiate first SPI transfer
      "ldi    r16, 0xff\n\t"
      "out    0x2e, r16\n\t"
      "rjmp   waitForSPIData\n\t"  // jump for waiting the data to prime simultaneous transfer

    "SPItoScreenLoop:\n\t"
      // Read last byte from SPI
      "in     r17, 0x2e\n\t"
      // initiate next SPI transfer while we output to screen
      "out    0x2e, r16\n\t"

      // low nibble to PORTF high
      "in     r18, 0x11\n\t"
      "andi   r18, 0xf\n\t"
      "mov    r19, r17\n\t"
      "lsl    r19\n\t"
      "lsl    r19\n\t"
      "lsl    r19\n\t"
      "lsl    r19\n\t"
      "or     r18, r19\n\t"
      "out    0x11, r18\n\t"
      // high nibble to PORTD low
      "in     r18, 0x0b\n\t"
      "andi   r18, 0xf0\n\t"
      "mov    r19, r17\n\t"
      "lsr    r19\n\t"
      "lsr    r19\n\t"
      "lsr    r19\n\t"
      "lsr    r19\n\t"
      "or     r18, r19\n\t"
      "out    0x0b, r18\n\t"
      // Toggle ILI WR
      "cbi    0x08, 6\n\t"
      "sbi    0x08, 6\n\t"

      // Wait for SPI data
    "waitForSPIData:\n\t"
      "sbis   SPSR,SPIF\n\t"
      "rjmp   waitForSPIData\n\t"

      // Check if we are done
      "add    r20, __temp_reg__\n\t"
      "adc    r21, __temp_reg__\n\t"
      "cpi    r21,2\n\t" // test against 512
      "brne   SPItoScreenLoop\n\t"
      "cpi    r20,1\n\t" // test against 513 as we skip the first write to let us write to screen while waiting for SPI
      "brne   SPItoScreenLoop\n\t"
      :
      :
      : "r16", "r17", "r18", "r19", "r20", "r21"
    );