VHDL - JK Flip Flop

--- Author: Matej Arlović, 2018.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity jk_flipflop is
    port(
            J, K, set, cp: in STD_LOGIC;
            Q, Qn: out STD_LOGIC
        );
end jk_flipflop;

architecture Behavioral of jk_flipflop is
signal temp: STD_LOGIC;
begin
    process(cp)
    begin
        if(set = '1') then
            temp <= '1';
        elsif(cp'EVENT and cp = '0') then
            if(J = '0' and K = '0') then
                temp <= temp;
            elsif(J = '0' and K = '1') then
                temp <= '0';
            elsif(J = '1' and K = '1') then
                temp <= not(temp);
            else
                temp <= '1';
            end if;
        end if;
    end process;
    Q <= temp;
    Qn <= not(temp);
end Behavioral;

--- Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY jk_flipflop_w IS
END jk_flipflop_w;

ARCHITECTURE behavior OF jk_flipflop_w IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT jk_flipflop
    PORT(
         J : IN  std_logic;
         K : IN  std_logic;
         set : IN  std_logic;
         cp : IN  std_logic;
         Q : OUT  std_logic;
         Qn : OUT  std_logic
        );
    END COMPONENT;

   --Inputs
   signal J : std_logic := '0';
   signal K : std_logic := '0';
   signal set : std_logic := '0';
   signal cp : std_logic := '0';

    --Outputs
   signal Q : std_logic;
   signal Qn : std_logic;
   constant cp_period : time := 200 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: jk_flipflop PORT MAP (
          J => J,
          K => K,
          set => set,
          cp => cp,
          Q => Q,
          Qn => Qn
        );

   -- Clock process definitions
   cp_process :process
   begin
        cp <= '0';
        wait for cp_period/2;
        cp <= '1';
        wait for cp_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
        set <= '1';
        J <= '0';
        K <= '0';
      wait for 100 ns;
        set <= '0';
        J <= '0';
        K <= '0';
        wait for 100 ns;
        J <= '1';
        K <= '0';
        wait for 100 ns;
        J <= '0';
        K <= '1';
        wait for 100 ns;
        J <= '1';
        K <= '1';
        wait for 100 ns;
        J <= '0';
        K <= '0';
        wait for 100 ns;
        J <= '0';
        K <= '0';
      wait for 100 ns;
   end process;
END;