library ieee;

use ieee.std_logic_1164.all;

entity Registers is
    port (
        CPU_CLOCK   : in  std_logic;

        INTERRUPT   : in  std_logic;

        ACC_INPUT   : in  std_logic_vector (7 downto 0);
        ACC_OUTPUT  : out std_logic_vector (7 downto 0);
        ACC_CONTROL : in  std_logic;

        BCC_INPUT   : in  std_logic_vector (7 downto 0);
        BCC_OUTPUT  : out std_logic_vector (7 downto 0);
        BCC_CONTROL : in  std_logic;

        SG1_INPUT   : in  std_logic_vector (5 downto 0);
        SG1_OUTPUT  : out std_logic_vector (5 downto 0);
        SG1_CONTROL : in  std_logic;

        SG2_INPUT   : in  std_logic_vector (5 downto 0);
        SG2_OUTPUT  : out std_logic_vector (5 downto 0);
        SG2_CONTROL : in  std_logic;

        FLG_INPUT   : in  std_logic_vector (7 downto 0);
        FLG_OUTPUT  : out std_logic_vector (7 downto 0);
        FLG_CONTROL : in  std_logic;

        STP_INPUT   : in  std_logic_vector (15 downto 0);
        STP_OUTPUT  : out std_logic_vector (15 downto 0);
        STP_CONTROL : in  std_logic;

        CPC_INPUT   : in  std_logic_vector (15 downto 0);
        CPC_OUTPUT  : out std_logic_vector (15 downto 0);
        CPC_CONTROL : in  std_logic
    );
end entity Registers;


architecture RTL of Registers is

    -- constants

    constant c_StartStack   : std_logic_vector (127 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110111111111"; -- 65023
    constant c_StartAddress : std_logic_vector (127 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000"; -- 768

    -- main CPU
    signal W_ACC1_InputWire       : std_logic_vector (7 downto 0);
    signal w_ACC1_OutputWire      : std_logic_vector (7 downto 0);
    signal w_ACC1_ControlSignal  : std_logic;

    signal w_BCC1_InputWire       : std_logic_vector (7 downto 0);
    signal w_BCC1_OutputWire      : std_logic_vector (7 downto 0);
    signal w_BCC1_ControlSignal  : std_logic;

    signal w_SG11_InputWire       : std_logic_vector (5 downto 0);
    signal w_SG11_OutputWire      : std_logic_vector (5 downto 0);
    signal w_SG11_ControlSignal  : std_logic;

    signal w_SG21_InputWire       : std_logic_vector (5 downto 0);
    signal w_SG21_OutputWire      : std_logic_vector (5 downto 0);
    signal w_SG21_ControlSignal  : std_logic;

    signal w_FLG1_InputWire       : std_logic_vector (7 downto 0);
    signal w_FLG1_OutputWire      : std_logic_vector (7 downto 0);
    signal w_FLG1_ControlSignal  : std_logic;

    signal w_STP1_InputWire       : std_logic_vector (15 downto 0);
    signal w_STP1_OutputWire      : std_logic_vector (15 downto 0);
    signal w_STP1_ControlSignal  : std_logic;

    signal w_CPC1_InputWire       : std_logic_vector (15 downto 0);
    signal w_CPC1_OutputWire      : std_logic_vector (15 downto 0);
    signal w_CPC1_ControlSignal  : std_logic;

    -- interrupt CPU
    signal W_ACC2_InputWire       : std_logic_vector (7 downto 0);
    signal w_ACC2_OutputWire      : std_logic_vector (7 downto 0);
    signal w_ACC2_ControlSignal  : std_logic;

    signal w_BCC2_InputWire       : std_logic_vector (7 downto 0);
    signal w_BCC2_OutputWire      : std_logic_vector (7 downto 0);
    signal w_BCC2_ControlSignal  : std_logic;

    signal w_SG12_InputWire       : std_logic_vector (5 downto 0);
    signal w_SG12_OutputWire      : std_logic_vector (5 downto 0);
    signal w_SG12_ControlSignal  : std_logic;

    signal w_SG22_InputWire       : std_logic_vector (5 downto 0);
    signal w_SG22_OutputWire      : std_logic_vector (5 downto 0);
    signal w_SG22_ControlSignal  : std_logic;

    signal w_FLG2_InputWire       : std_logic_vector (7 downto 0);
    signal w_FLG2_OutputWire      : std_logic_vector (7 downto 0);
    signal w_FLG2_ControlSignal  : std_logic;

    signal w_STP2_InputWire       : std_logic_vector (15 downto 0);
    signal w_STP2_OutputWire      : std_logic_vector (15 downto 0);
    signal w_STP2_ControlSignal  : std_logic;

    signal w_CPC2_InputWire       : std_logic_vector (15 downto 0);
    signal w_CPC2_OutputWire      : std_logic_vector (15 downto 0);
    signal w_CPC2_ControlSignal  : std_logic;

begin

    -- registers

    p_CPUSelector : process (INTERRUPT,
                                    ACC_INPUT, w_ACC1_OutputWire, w_ACC2_OutputWire, ACC_CONTROL,
                                     BCC_INPUT, w_BCC1_OutputWire, w_BCC2_OutputWire, BCC_CONTROL,
                                     SG1_INPUT, w_SG11_OutputWire, w_SG12_OutputWire, SG1_CONTROL,
                                     SG2_INPUT, w_SG21_OutputWire, w_SG22_OutputWire, SG2_CONTROL,
                                     FLG_INPUT, w_FLG1_OutputWire, w_FLG2_OutputWire, FLG_CONTROL,
                                     STP_INPUT, w_STP1_OutputWire, w_STP2_OutputWire, STP_CONTROL,
                                     CPC_INPUT, w_CPC1_OutputWire, w_CPC2_OutputWire, CPC_CONTROL) is begin

        w_ACC1_ControlSignal <= ACC_CONTROL;
        w_ACC1_InputWire     <= ACC_INPUT;
        ACC_OUTPUT              <= w_ACC1_OutputWire;

        w_BCC1_ControlSignal <= BCC_CONTROL;
        w_BCC1_InputWire     <= BCC_INPUT;
        BCC_OUTPUT             <= w_BCC1_OutputWire;

        w_SG11_ControlSignal <= SG1_CONTROL;
        w_SG11_InputWire     <= SG1_INPUT;
        SG1_OUTPUT           <= w_SG11_OutputWire;

        w_SG21_ControlSignal <= SG2_CONTROL;
        w_SG21_InputWire     <= SG2_INPUT;
        SG2_OUTPUT           <= w_SG21_OutputWire;

        w_FLG1_ControlSignal <= FLG_CONTROL;
        w_FLG1_InputWire     <= FLG_INPUT;
        FLG_OUTPUT           <= w_FLG1_OutputWire;

        w_STP1_ControlSignal <= STP_CONTROL;
        w_STP1_InputWire     <= STP_INPUT;
        STP_OUTPUT           <= w_STP1_OutputWire;

        w_CPC1_ControlSignal <= CPC_CONTROL;
        w_CPC1_InputWire     <= CPC_INPUT;
        CPC_OUTPUT           <= w_CPC1_OutputWire;

        if INTERRUPT = '1' then
           w_ACC2_ControlSignal <= ACC_CONTROL;
            w_ACC2_InputWire     <= ACC_INPUT;
            ACC_OUTPUT              <= w_ACC2_OutputWire;

            w_BCC2_ControlSignal <= BCC_CONTROL;
            w_BCC2_InputWire     <= BCC_INPUT;
            BCC_OUTPUT             <= w_BCC2_OutputWire;

            w_SG12_ControlSignal <= SG1_CONTROL;
            w_SG12_InputWire     <= SG1_INPUT;
            SG1_OUTPUT           <= w_SG12_OutputWire;

            w_SG22_ControlSignal <= SG2_CONTROL;
            w_SG22_InputWire     <= SG2_INPUT;
            SG2_OUTPUT           <= w_SG22_OutputWire;

            w_FLG2_ControlSignal <= FLG_CONTROL;
            w_FLG2_InputWire     <= FLG_INPUT;
            FLG_OUTPUT           <= w_FLG2_OutputWire;

            w_STP2_ControlSignal <= STP_CONTROL;
            w_STP2_InputWire     <= STP_INPUT;
            STP_OUTPUT           <= w_STP2_OutputWire;

            w_CPC2_ControlSignal <= CPC_CONTROL;
            w_CPC2_InputWire     <= CPC_INPUT;
            CPC_OUTPUT           <= w_CPC2_OutputWire;
        end if;

    end process p_CPUSelector;

    e_ACC : entity work.CpuRegister
        port map (CLOCK => CPU_CLOCK, INPUT => w_ACC1_InputWire, OUTPUT => w_ACC1_OutputWire, UPDATE => w_ACC1_ControlSignal);

    e_BCC : entity work.CpuRegister
        port map (CLOCK => CPU_CLOCK, INPUT => w_BCC1_InputWire, OUTPUT => w_BCC1_OutputWire, UPDATE => w_BCC1_ControlSignal);

    e_SG1 : entity work.CpuRegister
        generic map (g_BitSize => 6)
        port map (CLOCK => CPU_CLOCK, INPUT => w_SG11_InputWire, OUTPUT => w_SG11_OutputWire, UPDATE => w_SG11_ControlSignal);

    e_SG2 : entity work.CpuRegister
        generic map (g_BitSize => 6)
        port map (CLOCK => CPU_CLOCK, INPUT => w_SG21_InputWire, OUTPUT => w_SG21_OutputWire, UPDATE => w_SG21_ControlSignal);

    e_FLG : entity work.CpuRegister
        port map (CLOCK => CPU_CLOCK, INPUT => w_FLG1_InputWire, OUTPUT => w_FLG1_OutputWire, UPDATE => w_FLG1_ControlSignal);

    e_STP : entity work.CpuRegister
        generic map (g_BitSize => 16, g_InitialValue => c_StartStack)
        port map (CLOCK => CPU_CLOCK, INPUT => w_STP1_InputWire, OUTPUT => w_STP1_OutputWire, UPDATE => w_STP1_ControlSignal);

    e_CPC : entity work.CpuRegister
        generic map (g_BitSize => 16, g_InitialValue => c_StartAddress)
        port map (CLOCK => CPU_CLOCK, INPUT => w_CPC1_InputWire, OUTPUT => w_CPC1_OutputWire, UPDATE => w_CPC1_ControlSignal);

    -- interrupt CPU

    e_ACC2 : entity work.CpuRegister
        port map (CLOCK => CPU_CLOCK, INPUT => w_ACC2_InputWire, OUTPUT => w_ACC2_OutputWire, UPDATE => w_ACC2_ControlSignal);

    e_BCC2 : entity work.CpuRegister
        port map (CLOCK => CPU_CLOCK, INPUT => w_BCC2_InputWire, OUTPUT => w_BCC2_OutputWire, UPDATE => w_BCC2_ControlSignal);

    e_SG12 : entity work.CpuRegister
        generic map (g_BitSize => 6)
        port map (CLOCK => CPU_CLOCK, INPUT => w_SG12_InputWire, OUTPUT => w_SG12_OutputWire, UPDATE => w_SG12_ControlSignal);

    e_SG22 : entity work.CpuRegister
        generic map (g_BitSize => 6)
        port map (CLOCK => CPU_CLOCK, INPUT => w_SG22_InputWire, OUTPUT => w_SG22_OutputWire, UPDATE => w_SG22_ControlSignal);

    e_FLG2 : entity work.CpuRegister
        port map (CLOCK => CPU_CLOCK, INPUT => w_FLG2_InputWire, OUTPUT => w_FLG2_OutputWire, UPDATE => w_FLG2_ControlSignal);

    e_STP2 : entity work.CpuRegister
        generic map (g_BitSize => 16)
        port map (CLOCK => CPU_CLOCK, INPUT => w_STP2_InputWire, OUTPUT => w_STP2_OutputWire, UPDATE => w_STP2_ControlSignal);

    e_CPC2 : entity work.CpuRegister
        generic map (g_BitSize => 16)
        port map (CLOCK => CPU_CLOCK, INPUT => w_CPC2_InputWire, OUTPUT => w_CPC2_OutputWire, UPDATE => w_CPC2_ControlSignal);

end architecture RTL;