Advertisement
Guest User

Untitled

a guest
Jan 17th, 2019
76
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VHDL 0.42 KB | None | 0 0
  1. begin
  2.  
  3.   --USER logic implementation added here
  4.   led_PROCESS : process (Bus2IP_Clk) is
  5.   begin
  6.       if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
  7.         if Bus2IP_Reset = '1' then
  8.           led_i <= (others => '0');
  9.         else
  10.           if Bus2IP_WrCE(0) = '1' then
  11.             led_i <= Bus2IP_Data(24 to 31);
  12.           end if;
  13.         end if;
  14.       end if;
  15.     end process led_PROCESS;
  16.  
  17.     LED <= led_i;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement