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Randune1

MUX2v16

Jan 12th, 2023 (edited)
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VHDL 0.32 KB | Source Code | 0 0
  1. entity MUX2V16 is
  2.     Port ( Sel : in  STD_LOGIC;
  3.            I0 : in  STD_LOGIC_VECTOR (15 downto 0);
  4.            I1 : in  STD_LOGIC_VECTOR (15 downto 0);
  5.            Y : out  STD_LOGIC_VECTOR (15 downto 0));
  6. end MUX2V16;
  7.  
  8. architecture Behavioral of MUX2V16 is
  9.  
  10. begin
  11.     Y <= I0 when Sel='0' else I1;
  12.    
  13.  
  14. end Behavioral;
  15.  
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