msp430f5529lp_cscia1_uart.c

#include <msp430f5529.h>

void main(void) {
    WDTCTL = WDTPW | WDTHOLD;   // Stop watchdog timer
    // MSP430x5xx and MSP430x6xx Family User's Guide 894 Page
    // USCI Initialization and Reset
    // The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is
    // automatically set, keeping the USCI in a reset condition.
    // When set, the UCSWRST bit resets the UCRXIE,
    // UCTXIE, UCRXIFG, UCRXERR, UCBRK, UCPE, UCOE, UCFE, UCSTOE, and UCBTOE bits, and sets
    // the UCTXIFG bit. Clearing UCSWRST releases the USCI for operation.
    UCA1CTL1 |= UCSWRST;        // USCI_A Reset
    UCA1CTL0 = 0;           // 1 Stop bit, Parity disabled, LSB First select, 8-bit data
    UCA1CTL1 |= UCSSEL__SMCLK;  // SMCLK 8Mhz - SMCLK drives high-speed peripherals.
                    // It is kept alive during LPM0 but disabled in LPM3, LPM4, and LPM5.
                    // LPM0 is the lowest power mode permissible during an active USB connection.
    UCA1BR0 = 0x41;         // N=80000000/9600.0 = 833.3333333333334
    UCA1BR1 = 0x03;         // INT(N) = 833 = 0x341
    UCA1MCTL |= UCBRS_3;        // round(0.3333333333334*8) = round(2.6666666672) = 3
    UCA1CTL1 &= ~UCSWRST;       // Initialize USCI_A
    UCA1IE |= UCRXIE;       // Enable USCI_A1 RX interrupt
    _EINT();
}

#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void) {
    if (UCA1IV & 0x04) {
        while (!(UCA1IFG & UCTXIFG));
        UCA1TXBUF = UCA1RXBUF;
    }
}