Coffee Fsm

library ieee;
use ieee.std_logic_1164.all;

entity F is
port(
    clk, input, areset: in std_logic;
    output: out std_logic_vector(2 downto 0)
);
end F;

architecture arch of F is

    type state_type is (A, B, C, D, E, F, G);
    signal state, prev_state: state_type;

    begin

    process(clk, areset)
        begin
        if areset='1' then state<=A;
        elsif(clk'event and clk='1') then
        case state is
            when A=>
            if(input='1') then
            state<=B;
            prev_state<=A;
            end if;
            when B=>
            if(input='1') then state<=C;
            else state<=A;
            end if;
            prev_state<=B;
            when C=>
            if(prev_state=B and input='1') then
            state<=D;
            elsif((prev_state=E or prev_state=F) and input='1') then
            state<=F;
            else state<=A;
            end if;
            -- don't calculate prev_state
            when D=>
            if(input='1') then state<=E;
            else state<=C;
            end if;
            -- don't calculate prev_state
            when E=>
            if(input='0') then
            state<=D;
            elsif(input='1' and prev_state=F) then
            state<=G;
            end if;
            prev_state<=E;
            when F=>
            if(input='1') then state<=G;
            else state<=C;
            end if;
            prev_state<=F;
            when G=>
            -- nothing happens
        end case;
        end if;
    end process;

    process(state, input)
        begin
        case state is
            when A=>
            output<="000";
            when B=>
            output<="001";
            when C=>
            output<="010";
            when D=>
            output<="011";
            when E=>
            output<="100";
            when F=>
            output<="101";
            when G=>
            output<="110";
        end case;
    end process;

end arch;