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Vulpes

my_st_mach

Vulpes
Dec 13th, 2011
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  1. -- this project is not a complete success, it is missing data manipulation (commented out) in the
  2. -- states var1 & var2 as seen below. To calculate the variance, as far as I can determine, there is
  3. -- not a plausible way w/o removing all my debugging code. (as I have done this in blind_st_mach.txt
  4. -- & I retain enough SLICEMs to build a bit file). However, in terms of visuality, I will submit this
  5. -- project up as the final draft.
  6. --
  7. -- Properties:
  8. --  inputs:
  9. --      left most button:
  10. --          reset - resets all info on the device, resetting the RAM, counters, displays, etc.
  11. --      second to left:
  12. --          state switch button. this button triggers a state switch flag, then waits for the
  13. --          user to remove their finger from the button, otherwise, it would venture into the
  14. --          next state & the button, still pressed, would call for the state to be switched
  15. --          again. This can be altered to an internal signal changing the state switch flag
  16. --          instead of a user's button, ie in the "hold steady" parts of each state (hold
  17. --          steady is only for debug purposes)
  18. --      switch vector:
  19. --          this is used to view values inside some 256 array, the general input
  20. --          source for debugging
  21. --  outputs:
  22. --      seven segment display:
  23. --          down near the end of the architecture is a set of processes that manipulate
  24. --          the seven segment display relying on 1 external input source "four_seg_disp".
  25. --      leds out:
  26. --          this array of 8 leds is a general purpose debugging tool, used for many different
  27. --          things up to 8 bits. sections of numbers are displayed (if they cannot fit) or
  28. --          any miscellaneous byte, depending on what is to be debugged.
  29. --  State machine:
  30. --      wait_st:
  31. --          in this state you are able to view the contents of the packet payload (up to
  32. --          256 addresses in memory). this state can be used to wait for an incoming packet
  33. --          to properly load up the RAM
  34. --      taly_st:
  35. --          this state goes through all the bytes in the payload & tallies up the frequency
  36. --          of each number inside TALY(). It also takes the sum of all the numbers, thereby
  37. --          calculating the mean. The mean in this project is not appropriate because it does
  38. --          not do a true divide. It merely assumes a payload size of 256 & bitshifts 8 places.
  39. --          A divide would prove to add more hardware & was not considered at this time.
  40. --      vari_st:
  41. --          this state was broken down into smaller states due to too complex operations
  42. --          happening.
  43. --      var1_st:
  44. --          first part of vari_st, this state takes all bin tallies, subtracts them from
  45. --          the mean, & places the absolute value in the respective VARI().
  46. --      var2_st:
  47. --          taking the variance mean, this state adds up the variances, taking the abs held
  48. --          in VARI(), squaring it, & adding it to the running sum.
  49. --      disp_st:
  50. --          mainly for debugging purposes, you can view the mean & variance, which are the
  51. --          stats desired from the operation. This state would be a good state to send off
  52. --          these calculations & await approval from external devices.
  53.  
  54.  
  55.  
  56. library IEEE;
  57. use IEEE.STD_LOGIC_1164.ALL;
  58. use ieee.std_logic_unsigned.all;
  59.  
  60.  
  61. entity FINAL_VHDL_MOD is
  62.     port(
  63.         clock           : in    std_logic;
  64.         reset           : in    std_logic;
  65.         btn_st_sw       : in    std_logic;
  66.         swtch_vec       : in    std_logic_vector ( 7 downto 0);
  67.         seg_disp        : out   std_logic_vector ( 6 downto 0);
  68.         byte_out        : out   std_logic_vector ( 7 downto 0);
  69.         digit_disp      : out   std_logic_vector ( 3 downto 0)
  70.     );
  71. end FINAL_VHDL_MOD;
  72.  
  73.  
  74. architecture fsm of FINAL_VHDL_MOD is
  75.  
  76.     type pkt_type is array (255 downto 0) of std_logic_vector (07 downto 0); -- so far, this can only handle packets of 256 bytes exactly
  77.     type ram_type is array (255 downto 0) of std_logic_vector (15 downto 0); --1 byte array ram type
  78.     type st_type is (wait_st, taly_st, var1_st, var2_st, disp_st); --state machine
  79.    
  80.     -- wait_st: the chip sits around, twiddling its thumbs, waiting for you to push GO
  81.     -- taly_st: the chip goes through all addresses in payload buffer in RAM
  82.         -- & tallies them in appropriate bin in RAM, also, mean is found in this step
  83.         -- (being sum of all bytes in buffer divided by x100 (bitshift 8)
  84.     -- vari_st: after  mean is determined, mean is subtracted from each tally bin
  85.         -- & the value "is squared"(not sure yet) & placed in another buffer. also, the
  86.         -- value is added to a running sum. running sum will then be averaged (bitshift 8)
  87.     -- disp_st: once  average variance is calculated, results are displayed in some form
  88.         -- as mean & avg. variance. perhaps a loop to get back to wait_st
  89.  
  90.     --four_seg_display:
  91.     signal seg_selector     :   std_logic_vector( 1 downto 0):= "00";
  92.     signal one_seg_disp     :   std_logic_vector( 3 downto 0);
  93.     signal four_seg_disp        :   std_logic_vector(15 downto 0);
  94.     --end four_seg_display
  95.    
  96.     signal PYLD         :   pkt_type; -- incoming packet payload
  97.     signal TALY         :   ram_type; -- tally bins, each number appearing in the payload
  98.     signal VARI         :   ram_type; -- variance of each tally bin, no this does not hinder fpga space like I thought it would
  99.     signal curr_st, next_st     :   st_type; -- states of state machine
  100.     signal st_sw_flag       :   std_logic := '0'; -- the flag that triggers the state switch. de-assign the button & reassign another switch to increase performance
  101.     signal mean_pre_div     :   std_logic_vector(15 downto 0); -- word size adding all values of all tallies together
  102.     signal vari_mean_pre_div    :   std_logic_vector(31 downto 0); -- running sum of each bin's variance
  103.     begin
  104.  
  105.     process(clock,reset,btn_st_sw)
  106.         variable payload_size   :   natural := 256; -- payload size. This number will be variable when actually implemented
  107.         variable data_runs  :   integer range 0 to 65535 := 0; -- counter with 16 bits of range, used universally
  108.         variable btn_psh_dly    :   integer range 0 to 8388607; -- clock cycles it takes for you to take your thumb off button
  109.         begin
  110.        
  111.         if (clock'event and clock = '1') then
  112.             if    (reset='1') then
  113.                 -- main reset protocols
  114.  
  115.                 PYLD(000) <= "01111010"; PYLD(001) <= "10100110"; PYLD(002) <= "00011001"; PYLD(003) <= "00001010"; PYLD(004) <= "11111110"; PYLD(005) <= "01000111"; PYLD(006) <= "01011101"; PYLD(007) <= "11001010"; PYLD(008) <= "00100001"; PYLD(009) <= "11010100"; PYLD(010) <= "11010101"; PYLD(011) <= "01011011"; PYLD(012) <= "10011000"; PYLD(013) <= "01111001"; PYLD(014) <= "01001110"; PYLD(015) <= "01000111";
  116.                 PYLD(016) <= "00000010"; PYLD(017) <= "01110001"; PYLD(018) <= "00101001"; PYLD(019) <= "00100000"; PYLD(020) <= "10111010"; PYLD(021) <= "10000000"; PYLD(022) <= "11101110"; PYLD(023) <= "11000001"; PYLD(024) <= "10100011"; PYLD(025) <= "01111010"; PYLD(026) <= "00001010"; PYLD(027) <= "01111111"; PYLD(028) <= "01110000"; PYLD(029) <= "01011010"; PYLD(030) <= "11011101"; PYLD(031) <= "00110110";
  117.                 PYLD(032) <= "11111101"; PYLD(033) <= "11001010"; PYLD(034) <= "00111101"; PYLD(035) <= "01111100"; PYLD(036) <= "01101100"; PYLD(037) <= "01101110"; PYLD(038) <= "01001001"; PYLD(039) <= "01011101"; PYLD(040) <= "01000101"; PYLD(041) <= "10111100"; PYLD(042) <= "00101001"; PYLD(043) <= "11011101"; PYLD(044) <= "11011011"; PYLD(045) <= "01100000"; PYLD(046) <= "10111001"; PYLD(047) <= "11011000";
  118.                 PYLD(048) <= "00101001"; PYLD(049) <= "01001100"; PYLD(050) <= "11111000"; PYLD(051) <= "01001111"; PYLD(052) <= "11001100"; PYLD(053) <= "11101001"; PYLD(054) <= "10101110"; PYLD(055) <= "00011111"; PYLD(056) <= "10101111"; PYLD(057) <= "01100011"; PYLD(058) <= "01101111"; PYLD(059) <= "11000000"; PYLD(060) <= "00000100"; PYLD(061) <= "01001101"; PYLD(062) <= "11110110"; PYLD(063) <= "11111011";
  119.                 PYLD(064) <= "10100000"; PYLD(065) <= "00110100"; PYLD(066) <= "01111000"; PYLD(067) <= "11011100"; PYLD(068) <= "01000101"; PYLD(069) <= "00001101"; PYLD(070) <= "10101111"; PYLD(071) <= "00100010"; PYLD(072) <= "10110111"; PYLD(073) <= "01010001"; PYLD(074) <= "00000000"; PYLD(075) <= "00010011"; PYLD(076) <= "00001001"; PYLD(077) <= "10111001"; PYLD(078) <= "11000111"; PYLD(079) <= "10100100";
  120.                 PYLD(080) <= "11110011"; PYLD(081) <= "11000000"; PYLD(082) <= "11101000"; PYLD(083) <= "01000000"; PYLD(084) <= "01011001"; PYLD(085) <= "00110001"; PYLD(086) <= "11011111"; PYLD(087) <= "11110001"; PYLD(088) <= "01001010"; PYLD(089) <= "10001111"; PYLD(090) <= "11001001"; PYLD(091) <= "01001110"; PYLD(092) <= "11000101"; PYLD(093) <= "01000000"; PYLD(094) <= "01001010"; PYLD(095) <= "10010101";
  121.                 PYLD(096) <= "01110100"; PYLD(097) <= "00001110"; PYLD(098) <= "00100111"; PYLD(099) <= "10001011"; PYLD(100) <= "00000100"; PYLD(101) <= "01011011"; PYLD(102) <= "10101000"; PYLD(103) <= "10110000"; PYLD(104) <= "00100110"; PYLD(105) <= "10101000"; PYLD(106) <= "10101011"; PYLD(107) <= "00101111"; PYLD(108) <= "11001101"; PYLD(109) <= "00011101"; PYLD(110) <= "10011000"; PYLD(111) <= "01000001";
  122.                 PYLD(112) <= "11011101"; PYLD(113) <= "00001100"; PYLD(114) <= "10100001"; PYLD(115) <= "10101010"; PYLD(116) <= "10111101"; PYLD(117) <= "00000001"; PYLD(118) <= "10100111"; PYLD(119) <= "11110000"; PYLD(120) <= "10001110"; PYLD(121) <= "00011110"; PYLD(122) <= "01000001"; PYLD(123) <= "10101000"; PYLD(124) <= "01011110"; PYLD(125) <= "00101011"; PYLD(126) <= "01111101"; PYLD(127) <= "10010101";
  123.                 PYLD(128) <= "00100010"; PYLD(129) <= "01000101"; PYLD(130) <= "01011110"; PYLD(131) <= "00100110"; PYLD(132) <= "00111110"; PYLD(133) <= "11110001"; PYLD(134) <= "10001110"; PYLD(135) <= "00000111"; PYLD(136) <= "10100101"; PYLD(137) <= "01100010"; PYLD(138) <= "10101011"; PYLD(139) <= "00011010"; PYLD(140) <= "01111111"; PYLD(141) <= "01110111"; PYLD(142) <= "01011011"; PYLD(143) <= "01011101";
  124.                 PYLD(144) <= "11111000"; PYLD(145) <= "11111010"; PYLD(146) <= "11110000"; PYLD(147) <= "00111011"; PYLD(148) <= "11111011"; PYLD(149) <= "00101111"; PYLD(150) <= "11010111"; PYLD(151) <= "10001010"; PYLD(152) <= "00110110"; PYLD(153) <= "10110110"; PYLD(154) <= "01100110"; PYLD(155) <= "11100111"; PYLD(156) <= "10000010"; PYLD(157) <= "00100100"; PYLD(158) <= "00001001"; PYLD(159) <= "10100001";
  125.                 PYLD(160) <= "01100011"; PYLD(161) <= "01010000"; PYLD(162) <= "10010111"; PYLD(163) <= "11000010"; PYLD(164) <= "10011001"; PYLD(165) <= "01011010"; PYLD(166) <= "11000100"; PYLD(167) <= "01111100"; PYLD(168) <= "00000101"; PYLD(169) <= "00011111"; PYLD(170) <= "01101001"; PYLD(171) <= "11111001"; PYLD(172) <= "11100111"; PYLD(173) <= "10001110"; PYLD(174) <= "10011010"; PYLD(175) <= "01100000";
  126.                 PYLD(176) <= "00001011"; PYLD(177) <= "00010110"; PYLD(178) <= "01000111"; PYLD(179) <= "00001101"; PYLD(180) <= "10111010"; PYLD(181) <= "10110011"; PYLD(182) <= "10000000"; PYLD(183) <= "10010011"; PYLD(184) <= "11011100"; PYLD(185) <= "11100110"; PYLD(186) <= "00001101"; PYLD(187) <= "00111110"; PYLD(188) <= "11010001"; PYLD(189) <= "00000010"; PYLD(190) <= "01000000"; PYLD(191) <= "10001010";
  127.                 PYLD(192) <= "01010010"; PYLD(193) <= "11010111"; PYLD(194) <= "00101001"; PYLD(195) <= "00100111"; PYLD(196) <= "01100010"; PYLD(197) <= "00011101"; PYLD(198) <= "01000100"; PYLD(199) <= "01100111"; PYLD(200) <= "00001101"; PYLD(201) <= "10011101"; PYLD(202) <= "10100001"; PYLD(203) <= "11101001"; PYLD(204) <= "01010100"; PYLD(205) <= "01111011"; PYLD(206) <= "10111001"; PYLD(207) <= "01011111";
  128.                 PYLD(208) <= "11100010"; PYLD(209) <= "11111110"; PYLD(210) <= "01010101"; PYLD(211) <= "00100101"; PYLD(212) <= "10110010"; PYLD(213) <= "11010101"; PYLD(214) <= "10110110"; PYLD(215) <= "00010001"; PYLD(216) <= "01001000"; PYLD(217) <= "01111000"; PYLD(218) <= "00100000"; PYLD(219) <= "10111001"; PYLD(220) <= "01111010"; PYLD(221) <= "01100000"; PYLD(222) <= "11110111"; PYLD(223) <= "10010101";
  129.                 PYLD(224) <= "01001111"; PYLD(225) <= "11000001"; PYLD(226) <= "10110001"; PYLD(227) <= "00011100"; PYLD(228) <= "11011100"; PYLD(229) <= "11110101"; PYLD(230) <= "01111000"; PYLD(231) <= "00110111"; PYLD(232) <= "00010110"; PYLD(233) <= "00100101"; PYLD(234) <= "11000001"; PYLD(235) <= "01001001"; PYLD(236) <= "01000001"; PYLD(237) <= "10000100"; PYLD(238) <= "10110001"; PYLD(239) <= "10010011";
  130.                 PYLD(240) <= "00000101"; PYLD(241) <= "11101100"; PYLD(242) <= "10110110"; PYLD(243) <= "10110111"; PYLD(244) <= "11000111"; PYLD(245) <= "11011011"; PYLD(246) <= "10101110"; PYLD(247) <= "10101111"; PYLD(248) <= "10011111"; PYLD(249) <= "01011110"; PYLD(250) <= "11001001"; PYLD(251) <= "11101010"; PYLD(252) <= "00000001"; PYLD(253) <= "01000001"; PYLD(254) <= "00000000"; PYLD(255) <= "01001110";
  131.  
  132.                 --bits seeded with 4EE7356E
  133.  
  134.                 four_seg_disp <= "0000000000000000";
  135.                 btn_psh_dly := 0;
  136.                 byte_out <= "11111111";
  137.                 curr_st <= wait_st;
  138.                 next_st <= wait_st;
  139.                 mean_pre_div <= "0000000000000000";
  140.                 vari_mean_pre_div <= "00000000000000000000000000000000";
  141.             elsif (st_sw_flag = '1') then
  142.                 -- switching from current state to next state
  143.  
  144.                 four_seg_disp <= "1010000010100000";
  145.                 if (btn_psh_dly>0) then
  146.                     btn_psh_dly := btn_psh_dly - 1;
  147.                 else
  148.                     curr_st <= next_st;
  149.                     st_sw_flag <= '0';
  150.                 end if;
  151.             else
  152.                 -- in curr_st
  153.  
  154.                 if (btn_st_sw = '1') then
  155.                     -- button was pressed, prepare for state switch
  156.  
  157.                     st_sw_flag <= '1';
  158.                     btn_psh_dly := 8388607;
  159.                     data_runs := 0;
  160.                     case curr_st is
  161.                         when wait_st =>
  162.                             next_st <= taly_st;
  163.                             byte_out <= "00000010";
  164.                         when taly_st =>
  165.                             next_st <= var1_st;
  166.                             byte_out <= "00000100";
  167.                         when var1_st =>
  168.                             next_st <= var2_st;
  169.                             byte_out <= "00001000";
  170.                         when var2_st =>
  171.                             next_st <= disp_st;
  172.                             byte_out <= "00010000";
  173.                         when disp_st =>
  174.                             next_st <= wait_st;
  175.                             byte_out <= "00000001";
  176.                         when others  =>
  177.                             next_st <= wait_st;
  178.                             byte_out <= "00011111";
  179.                     end case;
  180.                 else
  181.                     -- I am in curr_st w/o interruption
  182.  
  183.                     case curr_st is
  184.                         -- this switch case here contains all details about algorithms performed
  185.  
  186.                         when wait_st =>
  187.                             -- not much going in on wait_st
  188.  
  189.                             four_seg_disp <= "00000001" & swtch_vec;
  190.                             byte_out <= PYLD(conv_integer(swtch_vec));
  191.                         when taly_st =>
  192.                             -- tallying up all bins, from 0 to <payload size
  193.  
  194.                             four_seg_disp <= mean_pre_div;
  195.                             byte_out <= TALY(conv_integer(swtch_vec))( 7 downto 0);
  196.                             if (data_runs < payload_size) then
  197.                                 mean_pre_div <= mean_pre_div + PYLD(data_runs);
  198.                                 TALY(conv_integer(PYLD(data_runs))) <= TALY(conv_integer(PYLD(data_runs))) + "00000001";
  199.                                 data_runs := data_runs + 1;
  200.                             else
  201.                                 --hold steady
  202.                             end if;
  203.                         when var1_st =>
  204.                             -- getting absolute value of VARI() - mean. first part of vari_st
  205.  
  206.                 --          if (data_runs < 256) then
  207.                 --              if (("00000000" & mean_pre_div(15 downto 8))>TALY(data_runs)) then
  208.                 --                  VARI(data_runs) <= (("00000000" & mean_pre_div(15 downto 8))-TALY(data_runs));
  209.                 --              else
  210.                 --                  VARI(data_runs) <= (TALY(data_runs)-("00000000" & mean_pre_div(15 downto 8)));
  211.                 --              end if;
  212.                 --              data_runs := data_runs + 1;
  213.                 --          else
  214.                 --              --hold steady
  215.                 --          end if;
  216.                             byte_out <= TALY(conv_integer(swtch_vec))( 7 downto 0);
  217.                             four_seg_disp <= VARI(conv_integer(swtch_vec));
  218.                         when var2_st =>
  219.                             -- taking variance of values held in VARI() & adding to variance mean
  220.  
  221.                 --          if (data_runs < 256) then
  222.                 --              vari_mean_pre_div <= vari_mean_pre_div + VARI(data_runs)*VARI(data_runs);
  223.                 --              data_runs := data_runs + 1;
  224.                 --          else
  225.                 --              --hold steady
  226.                 --          end if;
  227.                             four_seg_disp <= vari_mean_pre_div(15 downto 0);
  228.                             byte_out <= vari_mean_pre_div(23 downto 16);
  229.                         when disp_st =>
  230.                             -- displays final results of process
  231.  
  232.                             four_seg_disp <= mean_pre_div(15 downto 8) & vari_mean_pre_div(15 downto 8);
  233.                             byte_out <= VARI(conv_integer(swtch_vec))( 7 downto 0);
  234.                         when others =>
  235.                             four_seg_disp <= "0000011000000000";
  236.                     end case;
  237.                 end if;
  238.             end if;
  239.         end if;
  240.     end process;
  241.    
  242.     -------------------------------------------------------------------------------------
  243.    
  244.     -- the purpose of this lower section is to manage the four 7segment display, leaving
  245.     -- the upper part of the processes to only manage the four_seg_disp as the sole
  246.     -- variable. The signals associated with this section are marked above.
  247.  
  248.    
  249.     -- four_seg_display:
  250.     process (seg_selector,four_seg_disp)
  251.         begin
  252.         case seg_selector is
  253.             when "00" =>
  254.                 one_seg_disp <= four_seg_disp( 3 downto 0);
  255.                 digit_disp   <= "1110";
  256.             when "01" =>
  257.                 one_seg_disp <= four_seg_disp( 7 downto 4);
  258.                 digit_disp   <= "1101";
  259.             when "10" =>
  260.                 one_seg_disp <= four_seg_disp(11 downto 8);
  261.                 digit_disp   <= "1011";
  262.             when "11" =>
  263.                 one_seg_disp <= four_seg_disp(15 downto 12);
  264.                 digit_disp   <= "0111";
  265.             when others =>
  266.                 one_seg_disp <= "0000";
  267.                 digit_disp   <= "1111";
  268.         end case;
  269.        
  270.         case one_seg_disp is
  271.             when "0000" =>
  272.                 seg_disp <= "1000000";  --0
  273.             when "0001" =>
  274.                 seg_disp <= "1111001";  --1
  275.             when "0010" =>
  276.                 seg_disp <= "0100100";  --2
  277.             when "0011" =>
  278.                 seg_disp <= "0110000";  --3
  279.             when "0100" =>
  280.                 seg_disp <= "0011001";  --4
  281.             when "0101" =>
  282.                 seg_disp <= "0010010";  --5
  283.             when "0110" =>
  284.                 seg_disp <= "0000010";  --6
  285.             when "0111" =>
  286.                 seg_disp <= "1111000";  --7
  287.             when "1000" =>
  288.                 seg_disp <= "0000000";  --8
  289.             when "1001" =>
  290.                 seg_disp <= "0010000";  --9
  291.             when "1010" =>
  292.                 seg_disp <= "0001000";  --A
  293.             when "1011" =>
  294.                 seg_disp <= "0000011";  --B
  295.             when "1100" =>
  296.                 seg_disp <= "1000110";  --C
  297.             when "1101" =>
  298.                 seg_disp <= "0100001";  --D
  299.             when "1110" =>
  300.                 seg_disp <= "0000110";  --E
  301.             when "1111" =>
  302.                 seg_disp <= "0001110";  --F
  303.             when others =>
  304.                 seg_disp <= "1111111";
  305.         end case;
  306.     end process;
  307.    
  308.     process (clock)
  309.         variable seg_timout: integer range 0 to 65535;
  310.         begin
  311.         if (clock'event and clock = '1') then
  312.             if (seg_timout=0) then
  313.                 seg_selector <= seg_selector + "01";
  314.             end if;
  315.             seg_timout:=seg_timout-1;
  316.         end if;
  317.     end process;
  318.     -- end four_seg_display
  319. end fsm;
  320.    
  321.    
  322.  
  323. -------------------------------------------------------------------
  324.  
  325.    
  326.  
  327. -------------------------------------------------------------------
  328.  
  329.  
  330.  
  331. NET "clock"             LOC = "P54"; # Bank = 2,  Pin name = IO_L5N_2/D3/Gclock31, Sch name = clock1
  332. NET "reset"             LOC = "P69"; # Bank = 2, Pin name = IP,                   Sch name = BTN0
  333. NET "btn_st_sw"             LOC = "P48"; # Bank = 2, Pin name = IP_L3N_2/VREF_2       Sch name = BTN1
  334.  
  335.  
  336. NET "seg_disp<1>"           LOC = "P16"; # Bank = 3, Pin name = IO_L5P_3/Gclock22,     Sch name = CB
  337. NET "seg_disp<0>"           LOC = "P25"; # Bank = 3, Pin name = IO_L8P_3,            Sch name = CA
  338. NET "seg_disp<2>"           LOC = "P23"; # Bank = 3, Pin name = IO_L7N_3/Gclock27      Sch name = CC
  339. NET "seg_disp<3>"           LOC = "P21"; # Bank = 3, Pin name = IO_L6N_3/Gclock25,     Sch name = CD
  340. NET "seg_disp<4>"           LOC = "P20"; # Bank = 3, Pin name = IO_L6P_3/Gclock24/TRDY2,Sch name = CE
  341. NET "seg_disp<5>"           LOC = "P17"; # Bank = 3, Pin name = IO_L5N_3/Gclock23/IRDY2,Sch name = CF
  342. NET "seg_disp<6>"           LOC = "P83"; # Bank = 1, Pin name = IO/VREF_1,           Sch name = CG
  343. #NET "dp"               LOC = "P22"; # Bank = 3, Pin name = IO_L7P_3/Gclock26,     Sch name = DP
  344.  
  345. NET "digit_disp<0>"     LOC = "P34"; # Bank = 3, Pin name = IO_L10P_3,           Sch name = AN1
  346. NET "digit_disp<1>"     LOC = "P33"; # Bank = 3, Pin name = IO_L9N_3,            Sch name = AN2
  347. NET "digit_disp<2>"     LOC = "P32"; # Bank = 3, Pin name = IO_L9P_3,            Sch name = AN3
  348. NET "digit_disp<3>"     LOC = "P26"; # Bank = 3, Pin name = IO_L8N_3,            Sch name = AN4
  349.  
  350. NET "byte_out<0>"       LOC = "P15"; # Bank = 3, Pin name = IO_L4N_3/GCLK21      Sch name = LD0
  351. NET "byte_out<1>"       LOC = "P14"; # Bank = 3, Pin name = IO_L4P_3/GCLK20      Sch name = LD1
  352. NET "byte_out<2>"       LOC = "P8";  # Bank = 3, Pin name = IO_L3N_3,            Sch name = LD2
  353. NET "byte_out<3>"       LOC = "P7";  # Bank = 3, Pin name = IO_L3P_3,            Sch name = LD3
  354. NET "byte_out<4>"       LOC = "P5";  # Bank = 3, Pin name = IO_L2N_3/VREF_3,     Sch name = LD4
  355. NET "byte_out<5>"       LOC = "P4";  # Bank = 3, Pin name = IO_L2P_3,            Sch name = LD5
  356. NET "byte_out<6>"       LOC = "P3";  # Bank = 3, Pin name = IO_L1N_3,            Sch name = LD6
  357. NET "byte_out<7>"       LOC = "P2";  # Bank = 3, Pin name = IO_L1P_3,            Sch name = LD7
  358.                                                                                                                        
  359. NET "swtch_vec<0>"      LOC = "P38"; # Bank = 2, Pin name = IP,                  Sch name = SW0
  360. NET "swtch_vec<1>"      LOC = "P36"; # Bank = 3, Pin name = IP,                  Sch name = SW1
  361. NET "swtch_vec<2>"      LOC = "P29"; # Bank = 3, Pin name = IO(3S100E)/IP(3S250E),Sch name = SW2
  362. NET "swtch_vec<3>"      LOC = "P24"; # Bank = 3, Pin name = IP                   Sch name = SW3
  363. NET "swtch_vec<4>"      LOC = "P18"; # Bank = 3, Pin name = IP,                  Sch name = SW4
  364. NET "swtch_vec<5>"      LOC = "P12"; # Bank = 3, Pin name = IP/VREF_3,           Sch name = SW5
  365. NET "swtch_vec<6>"      LOC = "P10"; # Bank = 3, Pin name = IO(3S100E)/IP(3S250E),Sch name = SW6
  366. NET "swtch_vec<7>"      LOC = "P6";  # Bank = 3, Pin name = IP,                  Sch name = SW7
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