class.h

/*
        +----------------------------------------------------------+
        | +------------------------------------------------------+ |
        | |  Quafios Kernel 1.0.1.               | |
        | |  -> Device Classification System.            | |
        | +------------------------------------------------------+ |
        +----------------------------------------------------------+

*/

// This file is part of Quafios 1.0.1 source code.
// Copyright (C) 2012  Mostafa Abd El-Aziz Mohamed.

// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.

// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.

// You should have received a copy of the GNU General Public License
// along with Quafios.  If not, see <http://www.gnu.org/licenses/>.

// Visit http://www.quafios.com/ for contact information.

/* ============================================================== */
/*                          Bus Codes                             */
/* ============================================================== */

#define BUS_GENESIS         0x00
#define BUS_HOST            0x01
#define BUS_MEMORY          0x02
#define BUS_PCI             0x03
#define BUS_ISA             0x04
#define BUS_IDE             0x05
#define BUS_IDE_CHANNEL         0x06
#define BUS_SCSI            0x07
#define BUS_DISK            0x08
#define BUS_PCMCIA          0x09
#define BUS_CARDBUS         0x0A
#define BUS_UNDEFINED           0xFF

/* ============================================================== */
/*                       PCI Class Codes                          */
/* ============================================================== */

#define BASE_PCI_PRE2           0x00
#define  SUB_PCI_PRE2_NOTVGA        0x00
#define  SUB_PCI_PRE2_VGA       0x01

#define BASE_PCI_STORAGE        0x01
#define  SUB_PCI_STORAGE_SCSI       0x00
#define  SUB_PCI_STORAGE_IDE        0x01
#define  SUB_PCI_STORAGE_FLOPPY     0x02
#define  SUB_PCI_STORAGE_IPI        0x03
#define  SUB_PCI_STORAGE_RAID       0x04
#define  SUB_PCI_STORAGE_OTHER      0x80

#define BASE_PCI_NETWORK        0x02
#define  SUB_PCI_NETWORK_ETHERNET   0x00
#define  SUB_PCI_NETWORK_TOKEN_RING     0x01
#define  SUB_PCI_NETWORK_FDDI       0x02
#define  SUB_PCI_NETWORK_ATM        0x03
#define  SUB_PCI_NETWORK_OTHER      0x80

#define BASE_PCI_DISPLAY        0x03
#define  SUB_PCI_DISPLAY_VGA        0x00
#define  SUB_PCI_DISPLAY_XGA        0x01
#define  SUB_PCI_DISPLAY_OTHER      0x80

#define BASE_PCI_MULTIMEDIA     0x04
#define  SUB_PCI_MULTIMEDIA_VIDEO   0x00
#define  SUB_PCI_MULTIMEDIA_AUDIO   0x01
#define  SUB_PCI_MULTIMEDIA_OTHER   0x80

#define BASE_PCI_MEMORY         0x05
#define  SUB_PCI_MEMORY_RAM     0x00
#define  SUB_PCI_MEMORY_FLASH       0x01
#define  SUB_PCI_MEMORY_OTHER       0x80

#define BASE_PCI_BRIDGE         0x06
#define  SUB_PCI_BRIDGE_HOST_TO_PCI 0x00
#define  SUB_PCI_BRIDGE_PCI_TO_ISA  0x01
#define  SUB_PCI_BRIDGE_PCI_TO_EISA 0x02
#define  SUB_PCI_BRIDGE_PCI_TO_MICRO    0x03
#define  SUB_PCI_BRIDGE_PCI_TO_PCI  0x04
#define  SUB_PCI_BRIDGE_PCI_TO_PCMCIA   0x05
#define  SUB_PCI_BRIDGE_PCI_TO_NUBUS    0x06
#define  SUB_PCI_BRIDGE_PCI_TO_CARDBUS  0x07
#define  SUB_PCI_BRIDGE_OTHER       0x80

#define BASE_PCI_COMMUNICATION      0x07
#define  SUB_PCI_COMMUNICATION_SERIAL   0x00
#define  SUB_PCI_COMMUNICATION_PARALLEL 0x01
#define  SUB_PCI_COMMUNICATION_OTHER    0x80

#define BASE_PCI_PERIPHERALS        0x08
#define  SUB_PCI_PERIPHERALS_PIC    0x00
#define  SUB_PCI_PERIPHERALS_DMA    0x01
#define  SUB_PCI_PERIPHERALS_TIMER  0x02
#define  SUB_PCI_PERIPHERALS_RTC    0x03
#define  SUB_PCI_PERIPHERALS_OTHER  0x80

#define BASE_PCI_INPUT          0x09
#define  SUB_PCI_INPUT_KEYBOARD     0x00
#define  SUB_PCI_INPUT_DIGITIZER    0x01
#define  SUB_PCI_INPUT_MOUSE        0x02
#define  SUB_PCI_INPUT_OTHER        0x80

#define BASE_PCI_DOCKING        0x0A
#define  SUB_PCI_DOCKING_GENERIC    0x00
#define  SUB_PCI_DOCKING_OTHER      0x80

#define BASE_PCI_PROCESSOR      0x0B
#define  SUB_PCI_PROCESSOR_386      0x00
#define  SUB_PCI_PROCESSOR_486      0x01
#define  SUB_PCI_PROCESSOR_PENTIUM  0x02
#define  SUB_PCI_PROCESSOR_ALPHA    0x10
#define  SUB_PCI_PROCESSOR_POWERPC  0x20
#define  SUB_PCI_PROCESSOR_COPROCESSOR  0x40

#define BASE_PCI_SERIALBUS      0x0C
#define  SUB_PCI_SERIALBUS_FIREWIRE 0x00
#define  SUB_PCI_SERIALBUS_ACCESS   0x01
#define  SUB_PCI_SERIALBUS_SSA      0x02
#define  SUB_PCI_SERIALBUS_USB      0x03

/* ============================================================== */
/*                           Structutres                          */
/* ============================================================== */

typedef struct {
    unsigned int bus;   // bus type.
    unsigned int base;  // base class.
    unsigned int sub;   // sub class.
} class_t;