aa

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity registr is
    Port ( bot1 : in  STD_LOGIC;
           bot2 : in  STD_LOGIC;
           bot3 : in  STD_LOGIC;
           bot4 : in  STD_LOGIC;
           led1 : out  STD_LOGIC;
           led2 : out  STD_LOGIC;
           led3 : out  STD_LOGIC;
           led4 : out  STD_LOGIC);
end registr;

architecture arch of registr is
---------------vars---------------
signal x: std_logic_vector(0 to 3) := "0000";
signal x_temp: std_logic_vector(0 to 3) := "0000";
signal q: std_logic := '1';
signal neq: std_logic := '0';

begin

    process(bot1, bot3, bot4)

    begin

        x <= (not bot1) & x(1) & x(2) & x(3);

        if (not bot4 = '1') then
            x <= "0000";
        elsif (not bot3 = '1') then
            x <= x(3) & x(0) & x(1) & x(2);
        end if;


    end process;

    led1 <= x(0);
    led2 <= x(1);
    led3 <= x(2);
    led4 <= x(3);

end arch;