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-- Company:
-- Engineer:
--
-- Create Date:    17:49:56 03/21/2019
-- Design Name:
-- Module Name:    licznik - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity licznik is
Port     ( clk_i : in std_logic;
           rst_i : in std_logic;
           led_o : out std_logic);
end licznik;

architecture Behavioral of licznik is
constant n : integer := 3;
-- constant n : integer := 50000000;
signal licznik : integer range 0 to n - 1 := 0;
signal clk_o: std_logic := '0';

begin
    process (rst_i, clk_i)
        begin
        if (rst_i = '1') then
            licznik <= 0;
            clk_o <= '0';
        elsif (rising_edge(clk_i)) then
            licznik <= licznik + 1;
            if (licznik = (n / 2)) then
                clk_o <= '1';
            elsif (licznik = n-1) then
                clk_o <= '0';
                licznik <= 0;
            end if;
        end if;
    end process;
led_o <= clk_o;
end Behavioral;