library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity JK is port(
    CLK : in std_logic;
    R : in std_logic;
    J,K : in std_logic;
    Q,NQ : out std_logic
);
end JK;

architecture JK_arch of JK is

signal q1: std_logic:='0';
signal nq1 : std_logic:='1';

begin
process(CLK,R)
begin
    if (R = '1') then
        q1 <= '0';
        nq1 <= '1';
    elsif (rising_edge(CLK)) then
        if (J = '1') then
            if (K = '1') then
                q1 <= not(q1);
                nq1 <= not(nq1);
            else
                q1 <= '1';
                nq1 <= '0';
            end if;
        else
            if (K = '1') then
                q1 <= '0';
                nq1 <= '1';
            end if;
        end if;
    end if;
    Q <= q1;
    NQ <= nq1;
end process;
end JK_arch;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity licz74193 is port(
    clk:in std_logic;
    r:in std_logic;
    en:in std_logic;
    out4:out std_logic_vector(3 downto 0);
    max:out std_logic
);
end licz74193;

architecture licz74193_arch of licz74193 is

component JK is port(
     CLK : in std_logic;
    R : in std_logic;
    J,K : in std_logic;
    Q,NQ : out std_logic
 );
end component;

signal v4 : std_logic_vector(3 downto 0);
signal nv4 : std_logic_vector(3 downto 0);
signal n_v4 : std_logic_vector(3 downto 0);
signal n_nv4 : std_logic_vector(3 downto 0);
signal rst : std_logic;

begin

stage0: JK port map (clk,rst,en,en,n_v4(0),n_nv4(0));
stage1: JK port map (nv4(0),rst,en,en,n_v4(1),n_nv4(1));
stage2: JK port map (nv4(1),rst,en,en,n_v4(2),n_nv4(2));
stage3: JK port map (nv4(2),rst,en,en,n_v4(3),n_nv4(3));

process(clk)
begin
    if (n_v4 = "0000") then
        max <= '1';
        --rst <= '1';
    else
        rst <= r;
end if;
end process;


v4 <= n_v4;
nv4 <= n_nv4;
out4 <= v4;

end licz74193_arch;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity licznik is port(
    clk:in std_logic;
    r:in std_logic;
    en:in std_logic;
    res8:out std_logic_vector(7 downto 0);
    m:out std_logic
);
end licznik;

architecture licznik_arch of licznik is

component licz74193 is port(
    clk:in std_logic;
    r:in std_logic;
    en:in std_logic;
    out4:out std_logic_vector(3 downto 0);
    max:out std_logic
);
end component;


signal result : std_logic_vector(7 downto 0);
signal n_result : std_logic_vector(7 downto 0);
signal maxi : std_logic := '0';
--signal maxi2 : std_logic := '0';
signal rst : std_logic := '0';

begin

stage0: licz74193 port map(clk,rst,en,n_result(3 downto 0));
stage1: licz74193 port map(clk,rst,maxi,n_result(7 downto 4));

result <= n_result;
res8 <= result;
--maxi2 <= maxi;

process(clk)
begin
if (n_result = "00010101") then
    rst <= '1';
    maxi <= '0';
elsif (n_result = "00001111") then
    rst <= '0';
    maxi <= '1';
else
    rst <= '0';
    maxi <= '0';
end if;
end process;


end licznik_arch;