mem

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all ;

ENTITY memory_1024x8 IS
    PORT( Address : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 ) ;
          DataIN : IN SIGNED( 7 DOWNTO 0 ) ;
          WR, RD, CS, CLK : IN STD_LOGIC ;
          DataOUT : OUT SIGNED( 7 DOWNTO 0 ) ) ;
END memory_1024x8 ;

ARCHITECTURE Behavior OF memory_1024x8 IS

    TYPE mem_array IS ARRAY( 0 TO 1023 ) OF SIGNED( 7 DOWNTO 0 ) ;
    SIGNAL mem_data : mem_array ;

BEGIN

    write_process : PROCESS( CLK )
    BEGIN
        IF CS = '1' THEN
            IF ( CLK'EVENT AND CLK = '1' ) THEN --sincronous writing
                IF WR = '1' THEN
                    mem_data( TO_INTEGER( UNSIGNED( Address ) ) ) <= DataIN ;
                END IF ;
            END IF ;
        END IF ;
    END PROCESS write_process ;

    read_process : PROCESS ( Address )
    BEGIN
        IF CS = '1' THEN
            IF RD = '1' THEN --asincronous reading
                    DataOUT <= mem_data( TO_INTEGER( UNSIGNED( Address ) ) ) ;
            END IF ;
        END IF ;
    END PROCESS read_process ;

END Behavior ;