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-- Company:
-- Engineer:
--
-- Create Date:    19:34:24 02/07/2019
-- Design Name:
-- Module Name:    MUX2_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX2_1 is
    port (Arith : in STD_LOGIC;
           Logic : in STD_LOGIC;
            sel : in std_logic_vector (2 downto 0);
            Gout : out STD_LOGIC
            );
end MUX2_1;

architecture Behavioral of MUX2_1 is

begin
process (Arith,Logic,sel)
begin

  if (sel = "000" or sel = "011" or sel = "001")  then
Gout <= Logic;
  else
Gout <= Arith;
  end if;
end process;
end Behavioral;