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adder4

Sep 25th, 2021
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VHDL 0.30 KB | None | 0 0
  1. entity Adder4 is
  2.     port ( A   : in Std_Logic_Vector(3 downto 0) ;
  3.            B   : in Std_Logic_Vector(3 downto 0) ;
  4.            RESULT : out Std_Logic_Vector(3 downto 0) );
  5. end Adder4;
  6.  
  7. architecture DataFlow OF Adder4 is
  8. begin
  9.    RESULT <= std_logic_vector( unsigned(A) + unsigned(B) );
  10. end DataFlow;
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